Hi Vinod,
There are two clock inputs for DDRMC module, one is HCLK, the other is CLK/CLK2x, CLK/CLK2X is always sourced by PLL1 in the MCG, and HCLK source is selectable (PLL0 or PLL1 with MCG_C11[PLLCS] ), When HCLK source is PLL1 ( both clocks are the same ) the DDRMC will run in SYNCHRONOUS Mode, Else it will run in ASYNCRONOUS Mode, so would you please help to clarify which mode DDRMC was running on your board? and how did you configure the PLL1 and PLL0? Thanks for your patience!
Have a great day,
Kan