MK66FN2M0 ADC conversion rate questions

[RadaD]

Hi everyone!

I am not sure, how to correctly interpret the information about maximum ADC conversion rates given in the reference manual and technical datasheet for the MK66FN2M0.

The technical datasheet says Table 31. in 3.6.1.1 that for 13-bit mode and lower resolutions, the maximum ADC clock frequency is 24 MHz. The attached foot note 4 then states, that "To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set [...]". Setting the ADHSC bit in CFG2 enables high speed mode, which adds 2 clk cylces to the conversion time, leading to 8 clock cycles for single conversion mode, long conversion disabled. However, according to the reference manual, the fastest clock source option for the ADC is Bus clock, which is 60 MHz in this case (alternate clock and asynch. clock are both slower). Since divider options are division by 1,2,4,8 (2,4,8,16 in Bus clock divided by two mode), the fastest "legal" clock for the ADC is 60 MHz dividid by 4, i.e., 15 MHz. The question now is: Is it necessary two enable high speed mode ( CFG2[ADHSC] ) at 24 Mhz only (probably not) or at which frequency does it become necessary? Can the ADC clock be 15 MHz with high speed mode disabled?

Thanks!

[RadaD]

I see, thank you.

[nxf77486]

Hello @RadaD ,

No, power consumption will be higher when the high-speed (CFG2[ADHSC) mode is activated.

[RadaD]

Are you saying that power consumption is lower if CFG2[ADHSC] is set?

[nxf77486]

Hi @RadaD ,

The set of the high-speed mode for the ADC (CFG2[ADHSC]) can be configure in order to achieve the client application goals by respecting the rules to use this module. In this case the client take the decision in order to use it or not in case it frequency is lower than 24 MHz for 13 bit or 12 MHz for 16 bit modes.

This decision will remain only in the client thinking also on the power consumption. So at the end is decision of the client to use or not and spend the extra two clock cycle or not.

[RadaD]

Thank you @nxf77486.

Can you give me an example of an application, where one would like to set CFG2[ADHSC], i.e., spend the extra two clock cycles, when a lower frequency than 24 MHz for 13 bit respectively 12 MHz for 16 bit is used?

[nxf77486 · Accepted solution]

Hi @RadaD ,

Regarding your questions:

Yes the CFG2[ADHSC] High speed conversion sequence select 2 additional ADCK cycles to a total conversion time, activated or not will depend on your application if you want to used it or not. But it is mandatory for 24 MHz for 13 bit mode and 12 MHz for 16 bit mode.

There is no need for an specific frequency to activate the high speed mode, only the mandatory 24 MHz and 12 MHz. This will depend on your application thinking on power consumption, the ADC calculator can work as a good guidance, but at the end it is no necessary to set CFG2[ADHSC] at clock frequencies >= 8MHz.

Yes the only frequencies that require CFG2[ADHSC] to be set are 24 MHz for 13 bit and 12 MHz for 16 bit. And is not necessary for the value between f_ADCLK max and f_ADCLK min.

[RadaD]

Thanks @nxf77486.

From my understanding, CFG2[ADHSC] adds 2 additional clock cycles to the total conversion time, in order to accommodate for high clock speeds. Why would I want to activate it at clock frequencies that do not requiere it?

This ADC calculator from the NXP website suggests that CFG2[ADHSC] has to be set for ADC clock frequencies >= 8 MHz. Is that incorrect?

The only frequencies that requiere CHF2[ADHSC] to be set are 24 MHz at 13bit (23.5 MHz at 13 bit do not requiere it?) and 12 Mhz at 16 bit and it is not necessary at any frequency between f_ADCLK_max and f_ADCLK_min at 12 bit, i.e., 1 MHz to 24 MHz?

[nxf77486]

Hello @RadaD ,

Regarding your question the high speed mode can be activated at any frequency there is no need for an specific frequency (only mandatory for the 24 Mhz in 13 bit mode case and 12 MHz for the 16 bit mode) rule in order to activate it. But you will need to take on account that the power consumption will be higher because of the use of highspeed mode.

So yes you can either activate the high-speed mode at 15 MHz or not.