Kinetis MKL03,exit VLPS ,in debug mode no need to reconfigure clock

[diegocolombo]

Hi to all the people in the community,
I have to do with VLPS mode ,for the first time.
I can say I do enter in VLSP because the power consumption goes very low (from mA to tens of uA and I still have to set floating pins to reduce it further).
Exiting from this mode for RUN, i notice some things need to be set:
timings from LPTMR clocked by 1 KHz LPO are unchanged ,but other peripheral TPM1 works in wrong way.During debug everything runs normally,as woken from ISR after Wait
I found some explanations about how to reconfigure MCG:
Solved: Re: How to set MCG to PEE right before any ISR runs from waking VPLS? - NXP Community
For sake of understanding i would like to take a look inside the MCG registers during debug,before and after VLPS sleep,but for doing this I need that the problem appears during debug as well.
Is it possible?Why this behaviour in debug?
Thanks for your attention 
Diego

[Celeste_Liu]

Hello @diegocolombo ,

I'm very sorry for the late reply. I've just come back from my vacation.
I wonder if there has been any progress on your issue. I noticed that there is an errata 8068 for KL03Z. I'm not sure if you have paid attention to it. You can refer to the following web page: Solved: Problems putting KL03 into VLPS and reducing power consumption - NXP Community

Hope it can help you. If you have any further questions for me, please do not hesitate to let me know.

BRs,

Celeste