Looking at KE1xF (or S32K14x)
PORTx->PCR[IRQC] allows an input pin to latch edges or levels which can then be read in PORTx->PCR[ISF] PORTx->ISFR. This is very handy to avoid missing transitions while software is busy with other activities.
However, it seems that this will produce in an interrupt (or DMA) if any pin on PORTx is configured to do so.
I've seen other (Cortex-M4) processors where masking of such interrupts is configurable on a per-pin (rather than per-port) basis. Is this level of control not available?
