KW31Z constantly resetting

[microfirm]

I'm bringing up a new virgin MKX31Z board. I have it configured the DCDC converter for auto buck mode.

I'm supplying the VDCDC_IN with 3.6V for an external supply.

The VDD_1P8OUT pin is sitting at 1.7V

The VDD_1P5OUT pin is sitting at 1.64V

The RESET_b line is constantly asserting a 100uS period. It goes high approx 2.5uS and stays lows for approx 97.5uS

I was trying to connect to it w/ a modified FRDM-KW41Z eval board with using the OpenSDA Interface when I found that the new board just sits there constantly driving the RESET_b signal.

There is no way to gain control over the uC with it constantly resetting.

I read through all I can to try and figure out why the reset line would be behaving that way and I can not find anything to help.

What can be going on?

[microfirm]

Here's an update, I'm pretty sure that the problems that I've been seeing is due to bad soldering of the uC to the board.

That big ground plane underneath the part makes it tricky to hand solder these parts onto a board.

The assembler used a hot plate and low temp solder but I'm pretty sure that it did not work as all 3 boards behave differently.

[microfirm]

Yes I had to cut a few jumper shorts and wire directly to the K20 signals.

I also tried using a JLINK debugging probe and still can not connect.

I've tried 3 different new boards and to my surprise they all power up with different

VDD_1P8OUT and VDD_1P5OUT levels.

The 1st board I listed above.

The 2nd had the 1P8 out sitting at 500mV and the 3rd is sitting at 2.3V

Shouldn't I expect that the default values of 1.8V and 1.5V be the virgin part outputs for the DCDC converter set up for Auto-Buck mode?

[microfirm]

Has anyone had any luck converting a Freedom Development FRDM-KW41Z into a debugging system able to connect to a virgin uC?

[BlackNight]

Hi Frank,

do you mean like in Debug External Processors with USBDM and Freedom Board | MCU on Eclipse ?

I don't think this is easily possible, because (on purpose?) the J12 jumper is isolating the OpenSDA from J9 on the FRDM-KW41Z:

This is *different* from other boards where the jmper is isolating the target CPU from the header (e.g. FRDM-KL25Z):

So on the FRDM-KW41Z board you would have to cut the line to the PTA1_SWD_CLK which is not that simple.

I hope this helps,

Erich

[gerardo_rodriguez]

A little late, but a detailed hardware workaround can be found at FRDM-KW41Z Development Platform Errata in the section 4) Incorrect routing of SWD clock for stand-alone debugger configuration. :smileyhappy:

[mjbcswitzerland]

Hi

This is normal behavior for a Kinetis that hasn't been programmed - it shouldn't stop you connecting to it and loading code.

Regards

Mark