KV58 (KV5x): BME2 - SRAM_U Access

[lsrbigfoot]

Bit Manipulation Engine 2 (BME)

In Section 24.3.2.2 (Decorated Load: Load-and-Set 1 Bit (LAS1)) of the detailed KV58 spec (KV5XP144M240RM.pdf), the document describes that the base address for accessing (LAS1s) SRAM_U is 0x2000_0000.

This section is the only one where I see SRAM_U mentioned.

Does the SRAM_U region exist in the KV58 memory map?

If yes, then what is the memory range or how can SRAM_U be accessed?

In the K10/K20, SRAM_U refers to the Upper SRAM bitband region (0x2000_0000 to 0x200F_FFFF).

However the KV58 has Data SRAM (DTCM0 and 1) allocated between 0x2000_0000 and 0x2001_FFFF.

Does this mean that the upper DATA SRAM (DTCM1?) can be bit-banded?

[xiangjun_rong · Accepted solution]

Hi,

As you know that the BME(Bit Manipulation Engine 2) can operate the AND, OR, XOR, BFI, Clear One Bit, Set one Bit, bit Field Extract instructions, all the instructions can convert to read-modify-write operation.

For KV5X family, the BME address ranges from 0x4000-0000 to 0x4010-0000, the space is 1MB, all the peripheral are located in the BME range. The 1MB space supports all the BME operation.

The Data RAM is located at 0x2000_0000–0x2001_FFFF, you can save all the variables to the space.  it is not in the range of BME space, but the two instructions: load-and-clear 1 bit, Load-and-Set 1 Bit can support the space.

Hope it can help you.

BR

XiangJun Rong