KV4x : CADC Triggering with External GPIO Input

[EmbedALM]

Hi ,

i want to bind CADC Trigger with rising edge of external input using X-bara Module.

i have bind xbarIN2 with ADC trigger....

to give input trigger on XBARIN2 pin i m generating PWM pulse and connect that pin with external jumper to XBARIN2 ..

so when PWM goes high it trigger ADC and when ADC reading are ready in ADC IRQ i m toggling one GPIO to measure time...and it almost shows 900 ns...

why its taking this much time...

earlier i tested ADC triggering with PWM (commented line)

it has given around 400 ns time to get the result in ADC IRQ..

why its taking some extra time in case of GPIO...and also there is no setting of rising edge...so is it getting triggered on level change..??

[xiangjun_rong]

Hi,

If you use PWM signal to trigger ADC via crossbar, the delay you measured via GPIO toggling in ADC ISR is about 400nS. If you use XBARIN2 pin to trigger ADC which is connected to the same PWM signal, the delay is about 900nS.

I suppose that the the XBARIN2 pin is connected a SCHMITT TRIGGERS, which can guarantee that the ADC triggering signal is a digital signal. The SCHMITT TRIGGERS leads to the delay.

Hope it can help you

BR

XiangJun Rong

[EmbedALM]

I want to bind the Cyclic-ADC with an external input (GPIO). The ADC should be triggered on the rising edge of the external input signal.

Expectation:
The total time duration from the rising edge of the external input to the ADC interrupt (ADC IRQ) should be approximately 400 ns.

Issue:
In my case, this duration is around 900 ns. To verify this, I have used an oscilloscope:

• Yellow: Represents the external input signal.
• Green: Represents a pulse (GPIO toggle) that I generate in the ADC IRQ after receiving the ADC result.

Based on this observation, I suspect that the Cyclic-ADC is not being triggered correctly on the rising edge of the external input.

Could you please help me verify if the Cyclic-ADC is configured correctly for triggering on the rising edge? Are there any additional steps or settings required to achieve the expected 400 ns duration?

[xiangjun_rong]

Hi,

I do not see the I/O cell structure for KV4x, this is the normal I/O cell structure for KE1x, I suppose that the I/O cell for KV4x has the similar structure.

There is a  Schmitt-Trigger module in the input path which I marked as red circle, which can guarantee that the output of Schmitt-Trigger module is a digital signal to protect the digital input circuit. The Schmitt-Trigger module can lead to large delay.

If you use PWM trigger via cross-bar, it does not pass the I/O cell, so it does not have the delay.

Hope it can help you

BR

XiangJun Rong

[EmbedALM]

Thank you for the clarification regarding the Schmitt-Trigger delay in the KV4x I/O cell structure. I have a few additional questions:

1. Are there any recommended practices or alternate configurations to reduce the Schmitt-Trigger delay while still using an external input GPIO as the ADC trigger?

2. Are there other trigger sources or alternate methods in the KV4x family that can achieve ADC triggering from an external GPIO without incurring significant delays?

3. If the delay cannot be eliminated or minimized effectively, could you recommend a different NXP microcontroller family that allows ADC triggering from an external GPIO with either no delay or minimal latency (e.g., within 400 ns)? I am open to switching to a controller that better suits this requirement."

[xiangjun_rong]

Hi,

As far as I know that each I/O cell for every MCU has the Schmitt-Trigger  circuit to protect the I/O cell.

BR

XiangJun Rong