KL28 SIRC power consumption abnormal

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KL28 SIRC power consumption abnormal

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liangliangma
Contributor II

Here is the situation, we are testing the KL28 power consumption on a board with only MCU, 10k ohm reset pull up register and VDD3.3V capacitor. The code does nothing but initialize the system clock and goes to VLPS mode in a dead loop. SIRC is enabled at 8MHz. FIRC, SOSC and SPLL are disabled. Every thing else on the board is at reset state. With SIRC disabled in low power stop mode the average current is 4.7uA as expected. But when SIRC enabled in low power stop mode the current increases to 200uA, it seems that SIRC costs near 200uA, several times higher than the number in the datasheet.

Is there any clue about this?

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jingpan
NXP TechSupport
NXP TechSupport

Hi,

 I use the SDK_2.2_FRDM-KL28Z\boards\frdmkl28z\demo_apps\power_manager as example. And only made a small change in SMC_SetPowerModeVlps().

status_t SMC_SetPowerModeVlps(SMC_Type *base)
{
    uint8_t reg;
    uint32_t backreg,backreg2;
    /* configure VLPS mode */
    reg = base->PMCTRL;
    reg &= ~SMC_PMCTRL_STOPM_MASK;
    reg |= (kSMC_StopVlps << SMC_PMCTRL_STOPM_SHIFT);
    base->PMCTRL = reg;
    backreg=SCG->SIRCDIV;
    SCG->SIRCDIV=0;
    backreg2=SCG->SIRCCSR;
//    SCG->SIRCCSR=backreg2&(~(1<<1));  //slow IRC disable in stop mode
    SCG->SIRCCSR=backreg2|7;  //slow IRC enable, in stop/vlp mode
    /* Set the SLEEPDEEP bit to enable deep sleep mode */
    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;

    /* read back to make sure the configuration valid before enter stop mode */
    (void)base->PMCTRL;
    __DSB();
    __WFI();
    __ISB();

    SCG->SIRCDIV=backreg;

    /* check whether the power mode enter VLPS mode succeed */
    if (base->PMCTRL & SMC_PMCTRL_STOPA_MASK)
    {
        return kStatus_SMC_StopAbort;
    }
    else
    {
        return kStatus_Success;
    }
}

 I measure the current, it seems ok.

Regards

Jing

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liangliangma
Contributor II

Hi,

Good to hear it works, but still not on my board. Here is the code I used to test, it does nothing but initializes the clock and running mode, and then goes to VLPS mode with interrupt disabled. The SIRCDIV3 is set to 2 here, but the current is the same whether it is 0 or 2. 

int main(void)
{
__disable_interrupt();

/* Enable SIRC at 8MHz, SIRC_DIV3 = 4MHz */
SCG->SIRCDIV = SCG_SIRCDIV_SIRCDIV1(0) + SCG_SIRCDIV_SIRCDIV2(0) +
SCG_SIRCDIV_SIRCDIV3(2);

SCG->SIRCCFG = SCG_SIRCCFG_RANGE_MASK;

/* Enable SIRC in STOP and Low power mode */
SCG->SIRCCSR = SCG_SIRCCSR_SIRCEN_MASK | SCG_SIRCCSR_SIRCSTEN_MASK |
SCG_SIRCCSR_SIRCLPEN_MASK;
while ((SCG->SIRCCSR & SCG_SIRCCSR_SIRCVLD_MASK) == 0) {
/* Wait for SIRC to stable */
}

/* Set mode to RUN mode and VLPS mode */
SMC->PMCTRL = SMC_PMCTRL_RUNM(0) + SMC_PMCTRL_STOPM(2);
while (SMC->PMSTAT != SMC_PMSTAT_PMSTAT(1)) {
/* Wait for system transitting to RUN mode */
}

/* Set Run mode with SIRC at DIVCORE = 4MHz, DIVSLOW = 4MHz */
SCG->RCCR = SCG_RCCR_DIVCORE(1) + SCG_RCCR_DIVSLOW(1) + SCG_RCCR_SCS(2);
while ((SCG->CSR & SCG_CSR_SCS_MASK) != SCG_CSR_SCS(2)) {
/* Wait for RUN mode clock transitting to SIRC */
}

/* Set VLPR mode with SIRC at DIVCORE = 4MHz, DIVSLOW = 1MHz */
SCG->VCCR = SCG_VCCR_DIVCORE(1) + SCG_VCCR_DIVSLOW(7) + SCG_VCCR_SCS(2);

/* Disable SOSC */
SCG->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK;

/* Disable FIRC */
SCG->FIRCCSR = SCG_FIRCCSR_FIRCERR_MASK;

/* Disable SPLL */
SCG->SPLLCSR = SCG_SPLLCSR_SPLLERR_MASK;

/* Allow VLP modes */
SMC->PMPROT = SMC_PMPROT_AVLP_MASK;

/* Set the SLEEPDEEP bit to enable deep sleep mode */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;

/* Change to VLPR mode */
/* Set mode to RUN mode and VLPS mode */
SMC->PMCTRL = SMC_PMCTRL_RUNM(2) + SMC_PMCTRL_STOPM(2);
while (SMC->PMSTAT != SMC_PMSTAT_PMSTAT(4)) {
/* Wait for system transitting to VLPR mode */
}

while (1) {
SMC->PMCTRL &= ~SMC_PMCTRL_STOPM_MASK;
SMC->PMCTRL |= SMC_PMCTRL_STOPM(2); /* VLPS */

/* read back to make sure the configuration valid before enter stop mode */
(void)SMC->PMCTRL;
__DSB();
__WFI();
}
}

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jingpan
NXP TechSupport
NXP TechSupport

Hi Linagliang,

I test your question on my FRDM-KL28 board. I didn't found any problem. I test it on the SDK_2.2_FRDM-KL28Z\boards\frdmkl28z\demo_apps\power_manager. It seems ok.

have you set SIRCDIV1,SIRCDIV2,SIRCDIV3 to 000?

Regards

Jing

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liangliangma
Contributor II

There is no difference if SIRCDIV3 is 0 or 2. SIRCDIV1 and SIRCDIV2 are always 0. Our plan is to keep SIRC and LPUART always on to avoid data losing in communication

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