Currently I'm doing the following loop in firmware. I'd like to offload the processor and do this directly in the hardware:
1. Drive GPIOx1 high and drive GPIOx2 low
2. Initiate a read on the ADC and wait for the conversion to complete
3. Add result of ADC to a running total
4. Drive GPIOx1 low and drive GPIOx2 high
5. Initiate a read on the ADC and wait for the conversion to complete
6. Subtract result of ADC from a running total
To move this into hardware, my thoughts are as follows, but I'm looking for guidance and/or gotchas:
- For the GPIO pins (steps 1 and 4) use a pair of TPM channels in PWM mode with 50% duty cycle, initialized so they run out of phase from one another
- Set up the ADC to trigger on a PWM transition (is that possible?). Alternatively, initialize LPTMR to have the same period as the PWMs and use that to trigger the ADC.
- Configure the ADC to write its output using DMA transfer.
- Set up some mechanism (not sure what's best) to stop the ADC after N samples have been written
- In the foreground, wait for the N samples to be written, then do the add / subtract operation (steps 3 and 6) in firmware.
Some questions:
- Is this a feasible approach?
- Is there a better / simpler / more idiomatic way to accomplish the same results?
- Is there a mechanism to notify the firmware that N samples have been written (either via polling or interrupt)?
- I have a spare analog inverter in my system.
