KL25 using LLWU: crazy microcontroller

[stefanomanca]

Hi, I put my kl25 in LLS mode, and I config LPTMR0 (clocked by LPO) as wake-up source, so I have two class of interrupt to config. I noted this: if the priority of LLWU is bigger than LPTMR0, the micro goes to "loop" in Cpu_INT_LLWInterrupt, it seems LLWU_F3_MWUF0 never is deleted, so it enters and exits continuously. But  if the priority of LLWU is smaller than LPTMR0 all works.

Very very strange.

Any idea?

Thank you.

[perlam_i_au]

In the reference manual for KL25, (I will use as example the reference manual attached) you will find on the section 7.3 Power modes, the table Table 7-1. Chip power modes where you will find the note below in reference to LLS state:

NOTE: The LLWU interrupt must not be masked by the interrupt

controller to avoid a scenario where the system does not fully

exit stop mode on an LLS recovery.

This in order to keep the LLWU interrupt with the appropriate priority to avoid the loop.

Have a nice day :P,
Perla

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[philip_drake]

When you recover from LLS with the LPTMR and the LLWU has higher priority you must clear the LPTMR pending interrupt in the LLWU ISR routine or you will get stuck in the LLWU isr loop. This is because the source of the wakeup is still present upon attempted exit from the LLWU ISR. This same phenomena will occur when recovering from VLLSx with the same priority stated.

The LLWU_F3_MWUF0 is a status flag in the LLWU module and a write to it will not clear the LPTMR flag.

In several of the bare-metal sample code downloads you can find in the llwu_isr this code.

LPTMR0_CSR |=  LPTMR_CSR_TCF_MASK;   // write 1 to TCF to clear the LPT timer compare flag

This will clear the LPTMR interrupt flag but it will not clear the LPTMR pending interrupt flag in the NVIC. 

If you added this statement with the appropriate interrupt number to the LLWU isr

NVIC_ICPR |= 1 << (irq%32);

then both the LPTMR interrupt flag in the LPTMR and the NVIC pending interrupt will be cleared.

If you do this write to the NVIC_ICPR flag to quickly after the LPTMR0_CSR write it may not clear.  This has to do with the serialization of the flag clearing.  You must clear the LPTMR flag, veryify it is clear then clear the NVIC ICPR flag for the LPTMR. 

If the write to  NVIC_ICPR is not done in the LLWU ISR upon exit from the LLWU ISR the LPTMR interrupt service routine will be fetched. Even though the LPTMR flag is cleared by the LLWU clearing the pending interrupt the NVIC will still have a pending flag and force the call of the LPTMR ISR.

Please Note: the act of taking the interrupt vector, clearing the flag if it is set and exiting the interrupt routine clears the Pending Interrupt flag in the NVIC_ICPR register. This is evident in the NMI isr.  There is no way to clear the NMI clear pending interrupt flag aside from entering and exiting the NMI interrupt service routine.

AN4503 touches on some of this.

I hope this helps

PDrake

[stefanomanca]

Hi Philip, thanks for your explanations. Many things I did not know, but I wonder if it is a particular behavior of KL family or all microcontrollers act like KL family? Where Do i find this class of technical information? ANYWAY, your answer do not explain why if the priority of LLWU is smaller than LPTMR0 all works (without to involve NVIC).

Thank you very much.