KL15 - DMA with SPI - Interbyte delay

[CiaranMacA_hkc]

Hi All,

On a KL15x we are using the SPI at 2Mhz (i.e. SPI periperhal clock / spi clk = 2 Mhz). The core is running at 48Mhz and the bus clock at 24Mhz. We are using the DMA to push data into the SPI tx register. It seems to work but there is a short, fixed length, delay between bytes. It amounts to around 250ns - or about 12 system clock cycles.

1. What can be the cause of this delay?

When the DMA writes to the SPI tx register, I assume that in one cycle that is shifted into the Tx buffer (which is used to shift out the data serially at the SPI clk). But instantly after moving the data to the Tx bufferthe SPI will assert its request to the DMA. My question boils down to asking how long will it take the DMA to resolve the request and read data from RAM and then write it back into the SPI Tx register. Bear in mind that the SPI is running at 2Mhz so it will take it 4micro seconds to shift out the full byte. This should give the DMA plenty of time to have retrieved and written the next byte. I don't understand the delay?

Thank you,

Ciarán

[martynhunt]

Hi Ciarán,

The behavior you are describing sounds normal. The SPI module will display small gaps between byte transfers.

The 250 ns is half a clock cycle of the clock driving the SPI module (2 MHz). The bus clock is not driving data shifts directly, it is the divided clock you set driving the module.

Could you post a screen shot of your measured SPI signals? Are you monitoring the SS line? If so, what do you see? The gap should be the same duration as SS high.

Thank you,

Martyn

[werneralmesberg]

After reading this thread, I suspected that I may encounter similar issues in KL25 or KL26, and therefore couldn't use SPI for an application (radio modulation) that requires a perfectly isochronous data stream. But then I ran a few small tests, just to be sure, and I couldn't see anything that looked like an inter-byte delay. My setup is as follows:

- KL25 or KL26 (both behaved identically),

- SPI0, master, with SPI clock = bus clock / 2 (i.e., maximum speed),

- 8 bit words, MSB first,

- no DMA, no FIFO,

- CPHA = 1, CPOL = 0,

- my code polls SPTEF and puts the next byte in the transmit buffer when SPTEF is set.

Was I just lucky to hit a configuration that doesn't have inter-byte delays or do KL25 and KL26 not have the issue at all (as long as the program keeps up, of course) ?

Thanks,

- Werner

[CiaranMacA_hkc · Accepted solution]

Martyn,

Thanks for your response. We discovered here that our problem was the phase was erroneously set the wrong way.

Thanks again and all the best,

Ciarán