KL03Z: External Core Clock & Sleep Modes

[sarastout-grand]

Hello,

I'm running a KL03 with an external clock at 6.144MHz. This external clock is clocking the core and the bus.

If I enter VLPS mode, the core clock is supposed to go to a deep sleep. How does this work with an external clock that continues to run? When I tried it, the code doesn't advance beyond the spot where the VLPS sleep mode was initiated. Is that normal? If so, why?

Thanks,

Sara

[mjbcswitzerland]

Sara

In VLPS (and other stop modes) the clock is stopped to the core but it doesn't mean that the "clock source" stops.

Regards

Mark

[sarastout-grand]

Hi Mark,

So, does that mean that even though the core clock is "stopped" in the VLPS mode, if it is running on the external clock it will not actually be "stopped"? In my experiments this does not seem to be true. Even though my external clock keeps running, it seems that the code stops executing until after I wake it up from VLPS mode, as if the core is still stopped.

When I was reading more carefully, it sounds like the core clock is "gated off" as opposed to "Stopped". I presume that is referring to the clock gate that is after the OUTDIV1 block in the Figure 5-1 of the user manual. If that is true, then even if the external clock is still running, it makes sense that the clock won't get out to where it is supposed to go. This seems consistent with what I'm seeing. Do you agree?

Thanks,

Sara

[mjbcswitzerland · Accepted solution]

Sara

Yes, that is what I mean with "the clock is stopped to the core" - it is gated off somewhere (most likely in the core itself).

There are also a few possibilities to stop certain clocks but let others run too (eg. IRC sources), which are configurable in the SIM or in the MCG (or other places, depending on exact chip being used).

Regards

Mark