KEA ZN8

[hanisamara]

Hello,

how can i calculate the startup time for the Keazn8? i use the internal clk supplies FLL in FEI mode. How long does it take for the FLL to stabilize?

thank alot

[Hui_Ma]

Hi

The Max. POR (power on reset) time (from the power VDD reach 1.8V to core start to execution the first instruction code) is 300us.

Wish it helps.

Have a great day,
Ma Hui
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[hanisamara]

Hi,

Thank you for your answer!

but what about the FLL? in the Datasheet they talked about some max. 2ms for the FLL to stabilize!! but if i mesure it, i become something about 27ms!! is it possible?

Thanks

[Hui_Ma]

Hi

The datasheet shows the Max. FLL acquisition time 2ms. While how do you measure the FLL set up time? The test way different may cause the incorrect result. Thank you for the attention.

Have a great day,
Ma Hui
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[hanisamara]

Hi,

i just measure the time difference between applying Vcc on the Controller (i.e on the FLL too) and any Outpin to give some data out! So i have in my main.c just the clock_init routine (i have the while loop in the routine, which will leave the loop till the FLL lock pin is not set) after that i set an outpin to high! here is the clock_init routine with the while loop.

void init_clk(){

    ICS_C1|=ICS_C1_IRCLKEN_MASK;                                                             /* Enable the internal reference clock*/

    ICS_C3= 0x90;                                                                            /* Reference clock frequency = 31.25KHz*/

    while(!(ICS_S & ICS_S_LOCK_MASK));                                                       /* Wait for FLL lock, now running at 40 MHz (1280 * 31,25Khz) */

    ICS_C2|=ICS_C2_BDIV(1);                                                                 /* BDIV=2, Bus clock = 20 MHz*/

    ICS_S |= ICS_S_LOCK_MASK;                                                                 /* Clear Loss of lock sticky bit */   

}

without the while loop it just take less than 1ms!

Thank you for the attention!

[Hui_Ma]

Hi

I got Kinetis team ICS IP owner feedback that:

The 2ms acquisition time  has nothing to do with the LOCK bit,

We did not implement a bit to reflect if the clock source is acquired, but from baces test and design point of view, 2ms is a high confidence time, personally, I think 1ms is enough for acquisition time.

The LOCK bit is the monitor of clock quality, if clock is stable for 20-29ms the bit is set, if the clock is unstable, the LOCK bit is clear.

That's why using  below code will add 20ms delay time.

while(!(ICS_S & ICS_S_LOCK_MASK));

Wish it helps.

Have a great day,
Ma Hui
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[hanisamara]

Hi,

Thank you very much.

That means the whole clock inittialization and stabilization/acquisition time is about 27ms! and i can not reduce it? Should i have the while-loop in the routine? is there no way to bypass this wait time?

Thank you for taking the time to help!

Have a nice day,

Hani

[Hui_Ma · Accepted solution]

Hi

Yes, if customer want to get the stable clock, it need to check the lock flag. We recommend customer to check that lock bit. Bypassing that time(checking lock flag) will add system risk.

Wish it helps.

Have a great day,
Ma Hui
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[Hui_Ma]

Hi

I do a same test at TRK-KEA8 board and get the similar test result.

If add ICS_S [LOCK] flag checking in clock initialization code, the ICS Fll lock flag set time will more than 20ms (same with your test result).

I will checking with KEA product team about this issue. Thank you for the patience.

Wish it helps.

Have a great day,
Ma Hui
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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