KE18F512VLH16 ECC RAM Single Bit Correction

[rseigle77]

I have a follow up question related to @sean_dvorscak's post the other day (KE1 ECC RAM Single Bit Corrrection).

@Celeste_Liu replied,
->> If implementing an optional scrub, please align the access according to the actual access size or scrub granularity, not blindly to the raw MCM_LMFAR value. Also don't use a fixed 4-byte access unless you first align the address appropriately and confirm the access size is valid.

Can MCM_LMFATR[PEFSIZE] be used to determine the access size? If so, can this be used in tandem with MCM_LMFAR to implement a read-correct-writeback operation? For example, if MCM_LMFATR[PEFSIZE] is 3'b000 indicating an 8-bit access, can I perform an 8-bit read from the address indicated by MCM_LMFAR then perform an 8-bit write to the same address to correct the error. Similarly, if MCM_LMFATR[PEFSIZE] is 3'b010 indicating a 32-bit access, can I perform a 32-bit write to the address indicated by MCM_LMFAR without worrying about alignment?

[Celeste_Liu]

Hello @rseigle77 ,

Regarding your question, I need to escalate it to our internal team for further investigation. According to our process, please provide the end application name.

Thanks for your cooperation.

BR

Celeste

[rseigle77]

Hi @Celeste_Liu, is there any update on this?

[Celeste_Liu]

Hello @rseigle77 ,

Sorry, I still haven't received a response from the internal yet.

I'll follow up with them again and make this my top priority. As soon as I hear anything back, I'll let you know right away.

BR

Celeste

[Celeste_Liu]

Hello @rseigle77 ，

Thanks for your patience. I got the reply from the internal.

ECC "correction" means returning corrected data to the CPU, not fixing the underlying bit stored in SRAM. Automatic repair requires a separate scrub/write-back mechanism.

The recommended flow to use software scrub:

• ECC corrects data on read.
• Single-bit error interrupt/status is raised. Refer to RM 6.3.1.1 Determining source of the interrupt. MCM_LMPECR[ER1BR]=1
• Software reads the fault address. MCM_LMPEIR[PEELOC] = 5'h08 - a 1-bit correctable ECC event from SRAM_L, MCM_LMFAR indicates fault address.
• Software rewrites the corrected value back to the same address.
• New ECC syndrome is generated and stored.

BR

Celeste

[rseigle77]

Thanks for the response @Celeste_Liu, but that does not answer my question regarding MCM_LMFATR[PEFSIZE]:

"Can MCM_LMFATR[PEFSIZE] be used to determine the access size? If so, can this be used in tandem with MCM_LMFAR to implement a read-correct-writeback operation? For example, if MCM_LMFATR[PEFSIZE] is 3'b000 indicating an 8-bit access, can I perform an 8-bit read from the address indicated by MCM_LMFAR then perform an 8-bit write to the same address to correct the error. Similarly, if MCM_LMFATR[PEFSIZE] is 3'b010 indicating a 32-bit access, can I perform a 32-bit write to the address indicated by MCM_LMFAR without worrying about alignment?"

[rseigle77]

Hi @Celeste_Liu  - P7 is the name of the end application.

[Celeste_Liu]

Hello @rseigle77 ,

I have seen your post. Let me spend some time investigating this issue, and I will get back to you once I have more information.

BR

Celeste