K82: L1 Code and System caches

[EugeneHiihtaja]

Hello !

In K82 SDk you have fsl_cache.c driver what manipulate with L1 Code and System caches.

But it never ever used in any SDK example .

Only pflash example ( erase/write internal Flash memory ) invalidate L1 code cache

(  L1CACHE_InvalidateCodeCache(); ), even cache is not enabled at all ( ? ).

 - Does this some K82 specific cache peripheral or it more like ARM generic ?

- At what point I should enable System and Code cache if I have MPU enabled environment ?

- In what other use cases I should enable/disable/invalidate both caches ?

- Is any cache manipulation need on case of go in/out to Low power modes ?

Is any application note exists about usage of this type of caches ?

Thank you !

Regards,

Eugene

[jingpan]

Hi,

Yes, you are right. Unprivileged access are not allowed to access PRIMASK and FAULTMASK in the special-purpose mask register.

Regards,

Jing

[jingpan]

Hi Eugene,

I think in the pflash example, disable cache has no effect to the whole flow. When erase/write flash, the SDK driver will copy related function to SRAM. As you know, SRAM is Non-cacheable. It only want to show customer a good habit to prevent data corruption. For example, when some data in flash is cached and other process want to erase that area, data corruption may happen.

K82 cache is similar to ARM generic. You can see that some paragraphs in the chapter is copy from ARMv7 Architecture Reference Manual.

Cache function is not conflict with MPU function. There is nothing special need to be take care.

In low power state, cache is also low power. It is only powered to retain data. You'd better flush the data and stop cache.

I'm afraid there isn't any AN for cache.

Regards,

Jing

[EugeneHiihtaja]

Hi Jing !

In my case I have enable MPU and WriteBuffer, L1 Code and System caches. I try to have better performance for some math operations . In MPU all execution from RAM is disabled and I have created special section where allocate all code

from flash drivers what should be executed.

Should I really disable WriteBuffer, Invalidate code and system caches before and/or after erase/write operations to flash memory ?

Also I have some interrupt driven peripherals and FreeRTOS and I found out that ,for avoid sudden reboot

, I should disable/enable all interrupts or almost all. In case writing operations, writing whole sector 4KB is not even possible, may be it take long time and reboot happens without any hardfault and etc.

asm volatile ("cpsid f"); // or
//asm volatile ("cpsid i");
result = FLASH_Erase(&s_flashDriver, destAdrss, pflashSectorSize, kFTFx_ApiEraseKey);
//asm volatile ("cpsie i"); // ror
asm volatile ("cpsie f");

The same with FLASH_Write()

What can be recommendation for handle interrupts while Flash erase/write operations ?

In my design I have used LLS3 low power mode.

What can be recommendation for handle Write buffer/L1 Code and System caches when I go in/resume to/from LLS3 mode ?

Thank you !

Regards,

Eugene

[jingpan]

Hi,

To your first question, I don't think it's necessary to disable cache and write buffer.

When you erase/write flash, you must disable all the interrupt. Because if interrupt happen, MCU will read the service code in flash. But the flash is not ready.

I also don't think you have to disable cache in LLS3 mode. Cache is in low power mode at that time. Data is still there. Of course, if you worry about it. You can close the cache and write buffer. It will not waste too much time.

Regards,

Jing

[EugeneHiihtaja]

Hi Jing !

May be it have sense to invalidate caches before LLS3 mode or I think it is not mandatory.

By the way, should I use total interrupt disabling/enabling couple   (asm volatile ("cpsid f");  asm volatile ("cpsie f");)

for protect Erase and Write functions only or Verify need protection as well ?

What Flash API mast be protected ?

Also I think "cpsid f / cpsie f" dosn't work with User privileges and I should switch to Supervisor one for be able to disable/enable interrupts ?

Regards,

Eugene