K66 180MHz?

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K66 180MHz?

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przemyslawostro
Contributor I

Hello,

I am trying to setup K66 to run with 180 MHz core clock. My question is: can I do it without external oscillator on EXTAL0, XTAL0 pins. I have external oscillator(32768Hz) on EXTAL32, XTAL32 pins. In reference manual I found that this kind of speed (180 MHz) can be achieved only with PLL. The problem is that transition to PEE or PBE mode is only possible from FBE mode? And OSCCLK clock (whcih can be only generated by external oscillator) is required in FBE mode ?

Kind regards

John

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przemyslawostro
Contributor I

Hi Jorge and Mark, thanks for your posts.

Unfortunately it still doesn't work. (It works when I setup PLL to frequency around 60MHz). Also I am using PK66F which pre-release version.

This is my setting procedure, did I forget about something:

  // Allow High Speed Run (HSRUN) mode (FLASH write forbidden, no firmware update!)

  SMC->PMPROT |= SMC_PMPROT_AHSRUN_MASK;

  //Enter HSRUN mode

  SMC->PMCTRL |= SMC_PMCTRL_RUNM(3);

  // switch on USB first

  SIM->SCGC3 |= (SIM_SCGC3_USBHS_MASK | SIM_SCGC3_USBHSPHY_MASK | SIM_SCGC3_USBHSDCD_MASK);

  SIM->SCGC4 |= SIM_SCGC4_USBOTG_MASK;

  // switch on USB 48MHz oscilator

  USB0->CLK_RECOVER_IRC_EN |= USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK;

  //select MCG Oscillator Reference to IRC48M

  MCG->C7 |= MCG_C7_OSCSEL(2);

  //ENTER FBE:

  MCG->C1 |= MCG_C1_CLKS(2);

  //MCG->C1 |= MCG_C1_FRDIV();

  MCG->C1 &= ~MCG_C1_IREFS_MASK;

  MCG->C6 &= ~MCG_C6_PLLS_MASK;

  MCG->C2 &= ~MCG_C2_LP_MASK;

  while((MCG->S & MCG_S_IREFST_MASK) != 0)

  {

    // wait until external reference is current source for the reference clock

    ;

  }

  while((MCG->S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT != 2)

  {

    // wait until the external reference clock is selected to feed MCGOUTCLK

    ;

  }

   //ENTER PBE:

  /* fMCGOUTCLK = (OSCCLK / PLL_R) × M / 2 - this is in new datasheet*/

  MCG->C5 = MCG_C5_PRDIV(2); // divide

  MCG->C6 |= MCG_C6_VDIV(4); // multiply

  MCG->C1 |= MCG_C1_CLKS(2);

  //MCG->C1 |= MCG_C1_FRDIV();

  MCG->C1 &= ~MCG_C1_IREFS_MASK;

  MCG->C6 |= MCG_C6_PLLS_MASK;

  MCG->C2 &= ~MCG_C2_LP_MASK;

  while((MCG->S & MCG_S_PLLST_MASK) == 0)

  {

    ;

  }

  while((MCG->S & MCG_S_LOCK0_MASK) == 0)

  {

    ;

  }

  //ENTER PEE:

  MCG->C1 = 0x20;

  while((MCG->S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT != 3)

  {

    ;

  }

  SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(1) | SIM_CLKDIV1_OUTDIV2(3) | SIM_CLKDIV1_OUTDIV3(3) | SIM_CLKDIV1_OUTDIV4(6);

//IT CRASHES EXECUTING CODE BELOW THIS LINE

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tsi-chung_liew
NXP Employee
NXP Employee

Here are the reference for setting up for HS run mode.

Using IRC48 as clock source:

SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0) |    // Core/system
   SIM_CLKDIV1_OUTDIV2(2) |    // Busclk
   SIM_CLKDIV1_OUTDIV3(4) |    // FlexBus
   SIM_CLKDIV1_OUTDIV4(7));    // Flash

    enter_hsrun();

    MCG_C11 &= ~MCG_C11_PLLCS_MASK; // clear the PLLSC bit to select PLL0

    // (48MHz / 6) * 45 = 360MHz (VCO)

    // Core = 360 / 2 = 180MHz

    MCG_C5 &= ~MCG_C5_PRDIV_MASK;

    MCG_C5 |= MCG_C5_PRDIV(5);

    MCG_C6 &= ~MCG_C6_VDIV_MASK;

    MCG_C6 |= MCG_C6_PLLS_MASK | MCG_C6_VDIV(0x1D);

    MCG_C7 &= ~MCG_C7_OSCSEL_MASK;

    MCG_C7 |= 2;

    MCG_C5 |= MCG_C5_PLLCLKEN_MASK;

Using 16MHz external Crystal:

SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0) |    // Core/system
   SIM_CLKDIV1_OUTDIV2(2) |    // Busclk
   SIM_CLKDIV1_OUTDIV3(4) |    // FlexBus
   SIM_CLKDIV1_OUTDIV4(7));    // Flash

    enter_hsrun();

#define CRYSTAL     0

#define CLK0_FREQ_HZ    16000000

#define PLL_0   1

#define PLL0_PRDIV_HS    2

#define PLL0_VDIV_HS    45

    // (16MHz / 2) * 45 = 360MHz (VCO)

    // Core = 360 / 2 = 180MHz

    MCG_C5 &= ~MCG_C5_PRDIV_MASK;

    fbe_pbe(CRYSTAL,CLK0_FREQ_HZ,PLL_0, PLL0_PRDIV_HS,PLL0_VDIV_HS);

    pbe_pee(CLK0_FREQ_HZ,PLL_0);

Regards,

TsiChung

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przemyslawostro
Contributor I

Hi,

It did work in most cases (sometimes it did not start after reset), so I started to modify the code and now I can access the MCU with debugger.

How can I reprogram the MCU?

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mjbcswitzerland
Specialist V

Hi

You must set CLKDIV1 register "before" switching the PLL output to be system clock otherwise the flash clock will be out or range and the operation immediately fail.

Regards

Mark

Kinetis: µTasker Kinetis support

K64: µTasker Kinetis FRDM-K64F support  / µTasker Kinetis TWR-K64F120M support  / µTasker Kinetis TWR-K65F180M support

For the complete "out-of-the-box" Kinetis experience and faster time to market

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Jorge_Gonzalez
NXP Employee
NXP Employee

Hello Przemyslaw Ostrowski:

Right now I don't have the board to test but you should achieve 180 MHz core clock without external oscillator (EXTAL0/XTAL0) by using the IRC48M (48 MHz Internal Reference Clock). Your comment is true about transitions, but in FBE mode the IRC48M is valid as external reference for the MCG clock module.


Regards!,
Jorge Gonzalez

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mjbcswitzerland
Specialist V

Hi All

The TWR-K65F120M has a 16 MHz crystal and it, or the IRC48M (divided by 3 to be also 16MHz), can be used as input to the PLL.

To achieve 180MHz the VCO output needs to be 360MHz (PLL output is VCO/2 and can be used directly as system clock). This requires a VCO multiplication factor of

22.5 and the closest possible is 22, giving a system clock of 176Mz.

In the case of the IRC48MHz, it can however be divided by 4 to supply the PLL input with 12MHz (8MHz...16MHz range), which then allows a x30 multiplication to achieve 360MHz VCO, and thus 180MHz system clock.

I am wondering why there is a 16MHz crystal on the TWR-K65F120M rather than a 12MHz crystal, which would also have allowed the maximum frequency to have been reached?

Regards

Mark

Kinetis: µTasker Kinetis support

K64: µTasker Kinetis FRDM-K64F support  / µTasker Kinetis TWR-K64F120M support  / µTasker Kinetis TWR-K65F180M support

For the complete "out-of-the-box" Kinetis experience and faster time to market

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