K65 IO state during power ramp

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K65 IO state during power ramp

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dkh
NXP Employee
NXP Employee

While the K65’s VDD is ramping (or off, even) what are the IOs doing? Tristated, weak pull-up/downs?

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dkh
NXP Employee
NXP Employee

The key to the default states is whether the part is above the POR threshold.

 

On power-up, the GPIO states are indeterminate until the Power On Reset is complete at about 1V or so – the chip will be in reset at this time and enable the default bit settings. On power-down, the LVD setting will generate a reset which will make the GPIO high impedance. At the falling POR threshold the GPIO can go back to indeterminate states. The region between POR and LVD thresholds will generate a reset and make the GPIO high impedance.

                                                                                                                                                     - John S

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