K65/66 180MHz

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adyr
Contributor V

Hi,

I am trying to get the K66 to run at 180MHz but it is not playing fair. I have also tried on the TWR-K65F180 board with the same problems.

I am using KDS3 PEx and KSDK1.3 to configure the clocks and running a project that it created. The code gets into SystemInit but the board resets when it switches to the PLL clock. If I select a PLL / system clock of 172MHz both my board and the TWR run fine but any higher and they fail.

I have configured all the other clocks in PEx to ensure they are in range for the requested clock.

The second issue is when the USB UTMI PHY PLL is enabled the code hangs waiting for the PLL to stabilise. I'm not sure if the two problems are related.

Is there a known problem with PEx generated clock initialisation code or the processors ability to run at 180MHz?

Best regards,

Adrian.

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isaacavila
NXP Employee
NXP Employee

Hello Adrian,

I do not know what is your configuration but here is a project for TWR-K65F180M board which is working in HSRUN mode at 180MHz, it is using PEx and KSDK 1.3. Remember to enable HSRUN mode in CPU component (In Allowed power modes section) and set System clocks as follows:

Clocks settings.jpg

I am attaching it as reference. I am adding debug_Console component and using UART0 (which uses system clock as its source clock instead of using UART2 which is default console port but it is using bus clock) so you can corroborate that this is working at 180MHz (You can set a breakpoint at CLOCK_SYS_GetUartFreq function and validad freq value).

System clock.jpg

For USB issue, as Mark commented, you need to supply 5V voltage to USB PHY module in order to get PLL stabilized, one issue related to USB PHY's PLL is the one shown here: https://community.freescale.com/message/536991#comment-536991

I hope this can help you!

Best Regards,

Isaac

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adyr
Contributor V

Thanks Mark and Isaac. Using your projects as a starting point it works. Changing back to my settings one-by-one I discovered the 180MHz issue was because I was setting the External bus speed to 20MHz. After some more searching I found something that said the maximum divider is 8. So for 180MHz the slowest External bus speed is 22.5MHz and that allows the clock setup to work.

The USB PHY PLL problem is also fixed by selecting the clock source as and External Crystal instead of an External Reference Clock even though my board is using a clock.

So I am now up and running with a basic setup.

Best regards,

Adrian.

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isaacavila
NXP Employee
NXP Employee

Hello Adrian,

I do not know what is your configuration but here is a project for TWR-K65F180M board which is working in HSRUN mode at 180MHz, it is using PEx and KSDK 1.3. Remember to enable HSRUN mode in CPU component (In Allowed power modes section) and set System clocks as follows:

Clocks settings.jpg

I am attaching it as reference. I am adding debug_Console component and using UART0 (which uses system clock as its source clock instead of using UART2 which is default console port but it is using bus clock) so you can corroborate that this is working at 180MHz (You can set a breakpoint at CLOCK_SYS_GetUartFreq function and validad freq value).

System clock.jpg

For USB issue, as Mark commented, you need to supply 5V voltage to USB PHY module in order to get PLL stabilized, one issue related to USB PHY's PLL is the one shown here: https://community.freescale.com/message/536991#comment-536991

I hope this can help you!

Best Regards,

Isaac

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mjbcswitzerland
Specialist V

Hi

Here I have the TWR-K65F180M running at 176MHz:

http://www.utasker.com/kinetis/TWR-K65F180M.html

I don't remember why 176MHz rather than 180MHz but I have attached a version for 180MHz in case you would like to see whether it works (I can't check on the HW since I am traveling and don't have this board with me) - then you could read the MCG registers to check the setup with what PE gives you.

The simulation attached shows that all clocks are good - make sure that you are using HIGH SPEED RUN mode to achieve the speed.

The USB PLL will only lock when you have the cable connected so that the USB part is also being supplied with the necessary voltages; you need to abort the USB initisation in case the PLL doesn't lock and do it later when the USB voltage is detected and present.

Regards

Mark