K60 UART FIFO Size Control

[markccrow]

I have researched and hunted for hours trying to find a way to set a UARTs RX and TX FIFO size with no luck whatsoever (even Processor Expert did not seem to generate code which set the FIFO depths).

Can anyone point me in the right direction?

Thanks

[sudhanshumehta]

Thanks for correct answer :-)

[ndavies · Accepted solution]

There isn't any way to change the size of the FIFOs. The sizes are read only. The PFIF0 register only reports the amount of FIFO built into the UART. The control bits in PFIFO only turn on and off the FIFOs.

In section 55.3.16 of the \K60P144M150SF3RM.pdf , the subnote states

TXFIFOSIZE bitfield: The reset value depends on whether the specific UART instance supports the FIFO and on the size of
that FIFO. See the Chip Configuration details for more information on the FIFO size supported for
each UART instance.
•
RXFIFOSIZE bitfield: The reset value depends on whether the specific UART instance supports the FIFO and on the size of
that FIFO. See the Chip Configuration details for more information on the FIFO size supported for
each UART instance.
•

In section 3.9.7.1 States

7. UART0 and UART1 contains 8-entry transmit and 8-entry receive FIFOs
8. All other UARTs contain a 1-entry transmit and receive FIFOs

[markccrow]

Thank you so very much.  I must have searched that manual 20 times and somehow never saw the key info you pointed out.  Of course, if you search for 'FIFO' you will get 4,567 hits...