We are trying to set up a very low power data logger and are building out (on paper) an architecture around the K32L2B series to see if they are the right fit. The core functionality of this device is to sample a 16-bit differential ADC channel at ~100 Hz, with relatively low sample-to-sample jitter, then store it to an external memory when a buffer fills. The power source will be a coin cell, so low power use is critical.
The basic design we are proposing is to trigger the ADC conversions off the LPTMR, then DMA the result to a buffer, then raise a CPU interrupt and ping-pong buffers when the buffer fills. Heavy use of VLP modes would help achieve low overall power.
This design has raised several questions related to the ADC:
- What is the expected power consumption to run the ADC internal asynchronous clock ADCK?
- What is the expected sampling jitter due to starting and stopping ADCK, if it is not continuously running?
- Would clocking from the VLPW 1 MHz bus clock be a better choice than using ADCK?
- Can the ADC actually run in VLPS mode if using its internal async clock? Manual Tables 7-1 and 7-2 say it can. Manual Section 23.5.11 says it won't.
- Is an ADC clock of 1MHz, derived from a 1 MHz bus clock (limited by VLP modes), legal to clock the ADC in 16b mode? Datasheet Table 56 says it isn't, but Datasheet Figures 23 and 24 show the ADC was characterized with a 1MHz clock.
- What is needed from the bandgap reference VREFV1 to serve the ADC? Is "bandgap enabled" sufficient? Low power buffer enabled? High power? Burning 1mA for the high-power buffer is not exactly easy to budget for in a system like this.
Thanks to anyone who responds to any of the above (rather detailed) questions.
