K20 72MHz Confusing/conflicting documentation about fast IRC frequency, as well as VLPR mode

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K20 72MHz Confusing/conflicting documentation about fast IRC frequency, as well as VLPR mode

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christeanm
Contributor II

Hi everyone,

I’m new here. Stuck with confusing/conflicting statements in Freescale’s documentation about VLPR mode, the clock frequency limits in that mode and IRC clock frequency. Currently I am developing with the MK20DX256VLL7, 72 MHz Kinetis K20 device in 100 LQFP package. Freescale’s support for Kinetis links to this community for support, so please help me understand what is going on.

I used these documents:

Kinetis Peripheral Module Quick Reference Guide Rev.2 08/2012

K20 Sub-Family Reference Manual K20P100M72SF1RM Rev. 1.1, Dec 2012

Please bare with me as I go though the statements that I’ve found:

Kinetis Peripheral Module Quick Reference Guide Rev.2 08/2012:

1) Section 4.1.2, page 44: “…and a fast IRC with a frequency of ~4 MHz (with a fixed divide by 2).”

I’m already confused here. When taking a look at the schematic of the MCG in section 24.1.1 on page 506 of the reference manual there is no fixed divide by 2 on the output of the fast internal reference clock. There is a /2^n with n being 0..7. This divider is set by MCG_SC[FCRDIV] which states a divide factor of 1, or 2^0 being the lowest. This means that the output of this divider is still at 4 MHz if MCG_SC[FCRDIV] is set to ‘0b000’. The description of the FCRDIV bit reinforces that by saying
the resulting frequency will be in the range 31.25 kHz to 4MHz.”

2) Section 4.1.3.2, page 47: “…To be able to move the MCU into the VLPR (or wait) mode, the MCG must be set in a low-power, low-frequency mode with MCGCLKOUT <= 2 MHz, This mode is provided by means of selecting the fast IRC when the MCG is set in BLPI mode.”

Actually this is conflicting as well since the reference manual specifically specifies <= 4MHz (see below)

K20 Sub-Family Reference Manual K20P100M72SF1RM Rev. 1.1, Dec 2012:

3) Section 5.3, diagram on page shows fast IRC being 4 MHz

Well that is clear, the actual clock frequency directly from the fast IRC is 4MHz, regardless what comes directly after.

4) Section 5.4.1, Table 5-1, page 166: “Internal Reference (MCGIRCCLK) | RUN mode: 30-40 kHz or 2MHz | VLPR mode: 4 MHz only  “

Why is there a difference between the max frequency of MCGIRCCLK in normal RUN and VLPR mode the latter having a higher clock frequency? That is counter intuitive.

5) Same table, pages 165 and 166: in VLPR mode the clocks for core, system, bus and MCGOUTCLK can be up to 4 MHz

6) Section 7.2, Table 7-1 on page 190 agreed with the above in describing the VLPR mode.

OK so here it states that in VLPR I must select the fast IRC, being 4 MHz for MCGOUTCLK. In addition I can choose any value for the FCRDIV bit since the MCGOUTCLK will be 4MHz at max. In addition the clock dividers for the core/system and bus can be set to ‘divide by 1’ as they are allowed to run at 4MHz maximum. (Flash of course only at 1 MHz).

7) Section 14.4.1, table 14-7, page 304: “transition 3 from RUN to VLPR: reduce system, bus and core frequency to 2 MHz or less”

Huh? I just figured out that it could be 4MHz. So what now?

8) Section 24.4.1.1, table 24-16, page 524, note 1: “If entering VLPR mode, MCG has to be configured and enter BLPE mode or BLPI mode with the 4 MHz IRC clock selected (C2[IRCS]=1).”

That is kind of strange. If I go into BLPE mode but set C2[IRCS] = 1 the C1[CLKS] is still set to the external clock. So MCGOUTCLK is taken from the external clock instead of the fast IRC at 4MHz. Shouldn’t it be that for VLPR mode you must always go into BLPI mode? Then again, can you even go there directly from BLPE? Not according to the MCG mode state diagram in section 24.4.1 on page 520.

So my questions:

  • Is there a fixed divide by 2 after the fast IRC (4 MHz)?
  • Which maximum frequencies do I need to set in VLPR mode for core/system and bus: 4MHz or 2MHz? I’m not looking for an answer like “go for 2MHz that’s safe”, but the actual reason.
  • What about the BLPE mode and VLPR? Is that even possible?
  • If using the fast IRC in normal RUN mode, what is the (max) frequency of MCGIRCCLK, 2MHz or 4MHz? And moreover, why?

edit: layout & typo

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2 Replies

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perlam_i_au
Senior Contributor I

Christean:

I am doing some research, please see below what I have found at this moment:

1) Yes, if you set MCG_SC[FCDIV] with divide factor of 1 you will get a ~4MHz output from the Fast IRC, the information in the reference manual “…and a fast IRC with a frequency of ~4 MHz (with a fixed divide by 2).” I have never noticed, but I am looking for information to understand why is this on the RM.

2) I know this kind of statements are always confusing and require to pay much attention. In this case you need to know about power modes transition and why. As is mentioned on the KQRUG you need to follow a specific order to change your power mode, in this case if you want to enter to VLPR you need to configure the MCG as BLPI (Baypassed low power internal) in order to get the frequency (2MHz or less), you can achieve this entering  this mode from allowed modes like:

  • VLPW (MCG is already on BLPI in this mode)
  • Run (Typical MCG configuration after reset for MCG is FEI (FLL engaged internal), then you can change MCG configuration to BLPI folowing the order of power mode changes, please review Figure 24-14. MCG mode state diagram on the refernce manual)
  • VLPS (MCG is disabled in this mode, you can configure it as BLPI and enabling again the output from MCG module allow you to enter to VLPR).

3) I did not get it, I guess this is only a reference for the next point, am I rigth?

4) Normal Run power mode is the default mode out of reset, to make this possible the MCG mode is FEI, this mode requires a 32kHz clock (Table 24-16. MCG modes of operation) and this is the reason for the minimum frequency limit mentioned on Table 5-1. Clock Summary, the maximum frequency limit of 2MHz is related to MCG transitions, if you want to get out from FEI you need to follow the path depicted on Figure 24-14. MCG mode state diagram and for 2 of these modes you need a 32kHz or 2MHz internal reference clk, check these modes on the Table 24-16. MCG modes of operation.

5) Yes, in this power mode (VLPR) you can use the dividers, PLL and FLL to generate other frequencies based on IRC or external clk sources.

6) You got it

7) If your micro controller is on RUN mode probably your clock source (not MCGIRCLK) will be at a higher frequency (than 4MHz), in order to ensure a correct clock transition and avoid the core hangs you need to prepare your microcontroller for clok frequency transition, the first step is slow your frequency to change the clock source to the one you will use on VLPR, the MCGIRCLK only can deliver 30-40kHz or 2MHz in RUN mode and this is why you have to slow for make the clock source change before enter VLPR mode.

8) This is related to the last point, when you want to enter to VLPR (or other modes) you need to prepare your clocks, not only as a safe way to change frequencies also to avoid the core hangs in case of a very fast change. In this specific situation you have to enable the fast IRC before actually use it because you will need a stable signal on the change.

Then just following your structure:

  • Is there a fixed divide by 2 after the fast IRC (4 MHz)? --> I am still looking for this
  • Which maximum frequencies do I need to set in VLPR mode for core/system and bus: 4MHz or 2MHz? I’m not looking for an answer like “go for 2MHz that’s safe”, but the actual reason.--> I guess this has been explained on the points above
  • What about the BLPE mode and VLPR? Is that even possible? --> Yes, only consider that you should use an external clock signal which achieve the same frequency specification (you can use an external clock to meet tolerance specifications)
  • If using the fast IRC in normal RUN mode, what is the (max) frequency of MCGIRCCLK, 2MHz or 4MHz? And moreover, why? --> at RUN mode MCGIRCLK will run up to 2MHz.

I hope you find this useful, please let me know if you want to discuss something about my answer, sometimes these topics are a bit tricky.


Have a nice day,
Perla Moncada

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269 Views
christeanm
Contributor II

Hello Perla Moncada

First of all thank you very much for taking the time to investigate and reply to my questions. After reading through your post some things have become clear, while others still confuse me. In addition I went through the relevant chapters of the reference manual again, and I took a very careful look at the diagram at page 506 of the reference manual. So let me summarize what I think to understand. Please correct me where I'm wrong.

We are dealing with two major systems here: the MCG mode transitions and the Power Mode transitions.

Regarding the power modes I understand that:

  • One can transition from RUN into VLPR
  • Before entering VLPR all clocks in MCG must already be set within the limits of that power mode
  • In VLPR the requirements are:

      Clock source and frequency

    • Use IRC 4MHz clock as source or 4 MHz external clock
    • If using internal fast clock you need the MCG to be in BLPI
    • If using an external clock or system oscillator you need the MCG to be in BLPE
    • This external clock must be 4 MHz as well
    • If the external clock is possible, it means that note 1 at page 532 or the reference manual is incorrect by saying that you must use the fast IRC. Since you cannot enter VLPR with fast IRC selected and be in MCG BLPE mode at the same time.


           Main clock frequencies in VLPR

    • In VLPR the maximum frequency is 4MHz for a) core/system clock b) FlexBus clock and c) Bus clock.
    • In VPLR the maximum frequency is 1 MHz for the Flash clock
    • These clocks are all taken from MCGOUTCLK through a divider.
    • This also means that the documentation is wrong saying about those frequencies at in the sections referenced in my original post at 2) and 7) specifying 2 MHz max, since the undivided frequency of MCGOUTCLK can be up to 4 MHz


          MCG modes and VLPR

    • When in VLPR mode there cannot be changes in MCG mode to a non low power mode, i.e. any mode not being BLPI or BLPE.
    • As far as I understand you cannot go from BLPI to BLPE directly, only via BLPE → FBE → FBI → BPLI
    • So while in VLPR you cannot change from BLPI to BLPE or vice versa
    • In BLPI and BLPE the FLL and PLL are disabled so you cannot use them. The only way to get a lower frequency than 4 MHz is by setting MCG_SC[FRDIV] which is a divider specific for the fast IRC.

Regarding the MCG and its modes I understand that:

  • You can only get from one MCG mode to another as specified by Figure 24-14 MCG mode state diagram.
  • In VLPR MCGIRCCLK can be 4 MHz only
  • This means that if you want to use that clock you must set MCG_SC[FRDIV] to “divide by 1” and thus MCGOUTCLK can only be 4 MHz too (when using MCGIRCCLK)

  • Out of reset the MCU starts in FEI mode with FLL on, and 32kHz IRC selected. FLL output is set as MCGOUTCLK
  • From FEI you can go to either FEE or FBI.
    • If going to FEE the FLL input is taken from the system oscillator. In FEE the IRC frequency is not important for the FLL or MCGOUTCLK
    • If instead going to FBI the FLL is getting bypassed. Yet the FLL is not disabled and so its input must be in the FLL input range. This input can either be taken directly from the slow IRC at 32kHz or from the fast IRC which is 4 MHz by itself  but must be divided into a frequency low enough for the FLL input to accept.
    • The reference manual is wrong in table 24-16, page 522, description of FBI by saying the fast IRC is 2 MHz. The IRC is 4 MHz.

  • If you wish to use MCGIRCCLK:
    • This clock can only be 4 MHz in VLPR power mode. I cannot find the reason for this. If you'd want to divide the fast IRC to get a lower frequency for MCGOUTCLK the MCGIRCCLK if enables gets the same lower frequency.
    • In normal RUN mode the source for MCGIRCCLK can be either the slow or fast IRC. For discussions sake let’s say the IRCs are not used by any other part of the MCG. When selecting the slow IRC for MCGIRCCLK its frequency is identical to the  slow IRC which is 32kHz (±deviation errors). Yet when selecting the fast IRC, which is 4 MHz, I cannot find any reason in the clocking system why MCGIRCCLK cannot be taken directly and so be running at 4 Mhz.
    • I think the documentation is again wrong at page 166 (referenced in my original post at 4) ) by mentioning 2 MHz.


In summary

My best guess is that there is confusion with the writers and editors about the clocking system, which is possibly fueled by the statement found at 1) in my original post. This is about the fixed divide by two. I think that everywhere the documentation mentions 2 MHz it should be 4 MHz. The only possible exception I can find is if there is indeed a fixed divide by two. But then everywhere the documentation says 4 MHz it should be 2 MHz.

Can you confirm that my assumptions as listed above are correct or if not correct me where I'm wrong?