JTAG Chaining K10 with Xilinx Ultrascale FPGA

[lalit_verma]

Hi,

We are designing a VPX SBC board in which we are using K10 as IPMC. Now we have Xilinx FPGA also on the board.

Now, as per VPX standard connector, there is only one port of JTAG available on P0 connector.

So, we are planning to include Xilinx FPGA and K10 microcontroller in a single JTAG chain.

As, per Xilinx, Vivado can identify third part devices but need to import a csv file in Vivado which includes details like ID code etc:

My questions here are:

1. Does K10 IDE supports third party devices in the JTAG chain?

2. Please share the properties required for detecting K10 in Xilinx Vivado IDE like 

idcode

mask

irlen

name

I am attaching the example csv file required by Xilinx.

An early response will be highly appreciated.

Thanks,

Lalit

[lalit_verma]

Hi XiangJun Rong,

I can see that NXP supports PEmicro Multilink debuuger for K10.

Please find below the link which describes how we can do JTAG daisy chaining using Multilink with different devices like K10 MCU, FPGA etc:

https://www.pemicro.com/blog/index.cfm?post_id=136

Now, if there is an option for enabling JTAG daisy chaining in MCUXPresso, it will be really helpful for us.

Please let me know how to enable JTAG daisy chaining in MCUXPresso.

Thanks,

Lalit

[xiangjun_rong]

Hi,

As you pointed out that the probe devices such as J-Link and Multilink Universal support the JTAG daisy chain function, but the IDE such as MCUXPresso tools does not support the jtag daisy chain function.

BR

XiangJun Rong

[lalit_verma]

Hi NXP team,

Any response on this will he very helpful for us.

Thanks,

Lalit

[xiangjun_rong]

Hi, Lalit,

I suggest you use dedicated JTAG connector for both K10 and FPGA.

The JTAG chain requires IDE tools support for example Keil, MCUXPresso or IAR and the probe device support like Segger J-Link device, it is difficult.

Hope it can help you

BR

XiangJun Rong