Interrupt priority

[irmantasbudrys]

Hello,

I am using FRDM DEV BRD KEAZ128 and S32. 

I am using two interrupts, one from PIT every 1s another from ADC. For both interrupts priority level is 0. What will happen if interrupts would come in the same time or lets say ADC interrupt would come when PIT interrupt is doing somethig? Are where any sub priorities? Where can I find them? Where I can configer them? 

Best Regards,

IB

[mjbcswitzerland]

Hi

Cortex m0+ supports 4 priority levels (0..3).

If your interrupts use both 0 the second one will wait for the first to complete and then will be taken.

If you set the second with higher priority it can interrupt the first as long as the first doesn't (in its code) change the present interrupt mask level to block it, or set the global interrupt mask.

When working with interrupts that can pre-empt lower priority interrupts one needs to be very careful that the second interrupt can't disturb the first one's operation....

Regards

Mark

[santiago_lopez · Accepted solution]

Hi Irmantas

KEAZ128 has an ARM Cortex-M0+ which uses an ARMv6-M CPU. According with the Reference Manual (http://115.28.165.193/down/arm/arch/ARMv6-M_Architecture_Reference_Manual.pdf ) external interrupts such as the ADC and the PIT generates are prioritized by using the NVIC_IPRn registers. This is the first criteria the CPU takes into consideration. If both interrupts have the same priority, then the CPU will prioritize the interrupt with the lowest exception number. In the case of KEAZ128 it will be the ADC with the exception number 15. PIT0 and PIT1 are 22 and 23 respectively.

ARMv6-M implements preemption, so if an interrupt service routine (ISR) is being executed when another interrupt with higher priority arrives, the ISR of the new interrupt will execute first and return to the previous ISR upon completion.

Saludos

Santiago López