Hi,
Sorry for the so later reply.
The Analog part power supply and reference could affect the ADC conversion result.
Reduce a noise of ADC reference (VDDA, VSSA or VREFH, VREFL) as much as possible (any noise on ADC reference directly affects ADC digital results).
EXAMPLE: 12-bit mode, VREF = 3.0V±10mV, VADIN=2V
ADC result 1 = 2730 at 3.0V, ADC result 2 = 2720 at 3.01V, ADC result 3 = 2739 at 2.99V
Δ = 19
Below Hardware design way is using to reduce the noise:
- Use of linear regulator for analog power supply
- Place low value capacitors 100nF, 10nF (high dynamic capability, low ESR) as close as possible to the power supply pins (VDD, VSS and VDDA, VSSA) to avoid noise caused by PCB tracks,
- Place higher value capacitors 10uF, 47uF close to the power supply pins to reduce low frequency noise (power mains influence)
- Isolate digital and analog power supply lines by ferrite bits for higher frequency noise reduction (low impedance at low frequency and high impedance on higher frequency)
- If possible/available use separate digital and analog power supply (dependent on package/device/VREF pins availability).
NOTE: separate supplies for VDD and VDDA is not recommended (see specification in DS)
- Separate digital and analog parts on PCB
Will reduce capacitive coupling of analog and digital tracks
Will also reduce EMI because of distance
The noise of source could be:
- I/O pins crosstalk – capacitive coupling between I/Os
I/O signal tracks which passing close to each others – same layer of PCB
I/O signal tracks which crossing each other – different layers of PCB
- EMI from close circuits (PCB tracks can have antenna effect)
Below hardware design to reduce the source noise:
- Reduce crosstalk by proper grounding (place GND track between close passing analog and digital signals)
- Proper shielding reduces EMI
Note: Shielding does not mean grounding (avoid grounding current flow via shielding)
- Identify possible EMI sources and receptors and try to separate them (filters, grounding, shielding)
- Reduce the length of PCB tracks to the analog input to be measured (reduce parasitic LC components)
- Use shielding cables to ADC input when measured signal coming from distant locations (sensors etc.)
The ADC module configuration (software way) to enhance the ADC performance is:
1> Reduce ADC conversion clock frequency;
2> Enable hardware average;
The Kinetis SAR only defines static performance up to 12-bit accuracy. Ramp testing is prohibitively difficult beyond 12-bit accuracy, and although we have a capable test setup and alternative methods we could use for 16-bit linearity, the test times are so long that a full characterization of the ADC across all operating conditions and configurations is an impossible resource sink for our limited validation resources. That's why the K64 datasheet only provide ADC module with 12-bit mode data about TUE, DNL, INL and etc. parameters.
Thank you for the understanding.
I would recommend customer to using hardware average enable to enhance the ADC performance.
Wish it helps
Have a great day,
Ma Hui
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
