I am trying to use DMA for transferring data from UART1 to UART0 on the KL15. I am using DMA channel 1. My code for initializing the DMA is below.
void DMA_Init()
{
/* Enable the clock to DMA MUX and DMA */
SIM_SCGC6 |= SIM_SCGC6_DMAMUX_MASK;
SIM_SCGC7 |= SIM_SCGC7_DMA_MASK;
// Disable the DMA0 channel
DMAMUX0_CHCFG1 = 0x00;
// Clear pending errors or the done bit for channel 1
if (((DMA_DSR_BCR1 & DMA_DSR_BCR_DONE_MASK) == DMA_DSR_BCR_DONE_MASK)
| ((DMA_DSR_BCR1 & DMA_DSR_BCR_BES_MASK) == DMA_DSR_BCR_BES_MASK)
| ((DMA_DSR_BCR1 & DMA_DSR_BCR_BED_MASK) == DMA_DSR_BCR_BED_MASK)
| ((DMA_DSR_BCR1 & DMA_DSR_BCR_CE_MASK) == DMA_DSR_BCR_CE_MASK))
DMA_DSR_BCR1 |= DMA_DSR_BCR_DONE_MASK;
// Set Source Address for DMA (UART1_D register)
DMA_SAR1 = 0x4006B007;
// Clear the DCR bits
DMA_DCR1 &= ~(DMA_DCR_SSIZE_MASK | DMA_DCR_CS_MASK);//0x0202;
// Set the DMA configuration
DMA_DCR1 |= (DMA_DCR_SSIZE(1)
| DMA_DCR_DSIZE(1)
| DMA_DCR_CS_MASK
| DMA_DCR_ERQ_MASK
| DMA_DCR_EADREQ_MASK
);
// Set DMA byte counter
DMA_DSR_BCR1 = DMA_DSR_BCR_BCR(3);
// Set Destination Address (UART0_D)
DMA_DAR1 = 0x4006A007;
// Enable UART1 operation in the DMA source slot
DMAMUX0_CHCFG1 = 0x4;
// Enable the DMA MUX
DMAMUX0_CHCFG1 |= DMAMUX_CHCFG_ENBL_MASK;
}
This setup is passing only the first 3 bytes of data received at UART1. Which makes sense as I set the BCR to 3. My question is, is there any way to configure the DMA so that it is not dependent upon the counter. I want the DMA to transfer incoming byte at UART1 to UART0 as long as DMA request bit in UART1 is enabled. Can it be configured to work that way?