IEC 60730 RAM test backup area

[MLapaj]

Hi, 

I've got a question regarding RAM test functions from IEC60730 4.0 library for Cortex-M0+.

While using FS_CM0_RAM_AfterReset() and FS_CM0_RAM_Runtime() functions, can the tested memory area include the RAM test backup area or does the backup have to be excluded from tested addresses?

Let's suppose the tesed area is from 0x1FFFF000 to 0x20002FFF, which is the whole RAM area. Can the backup area overlap with tested area (e.g. can the backup area be placed at 0x1FFFF800 address, as long as it is reserved)?

[diego_charles]

Hi @MLapaj 

If the backup memory is inside the tested memory (ovelap),  the tests functions   probably  destroy the contents stored in the backup area for a certain block on a certain  in a iteration.  I will recommend to avoid overlapping.

Br,

Diego.

[MLapaj]

I don't mind the backup area contents being destroyed since it's reserved area anyway. What I am worried about is receiving false negative result of a test. Is there any chance of that happening? 

Or are there any other consequences to test area and backup area overlapping?

[diego_charles]

Hi @MLapaj ,

 I will consult  internally  to validate my reply to your inquiry. Could you let me know  the MCU that you are plannig to use with the library?

Thank you,

Diego.

[MLapaj]

Hi @diego_charles, 

It's being used only on Kinetis KE06 at the time. 

[diego_charles · Accepted solution]

Hi @MLapaj 

I have received feedback on the matter.

The backup memory  should not be placed inside of tested SRAM memory range.

Our suggestion to test all the SRAM range is to create a least two test interfaces, where the backup memory (for the first instance) will be placed in the second instance memory range and vice versa.

Thank you for your patience.

Regards,

Diego

[MLapaj]

I understand. Thank you for your help.