I2C

[deast]

Hello. Can someone please explain the I2C SPEC ranges? Especially for PCA9511, PCA9517, and PCA9548. Margins seem small. Thanks

[deast]

Thanks, Jose!

This is exactly what was needed. Very thorough.

Best,

Darcell E.

[reyes · Accepted solution]

Hi

I’m assuming you are referring to the I2C spec ranges in term of valid voltages for the communication (VIL/VIH). Please correct me if I’m wrong.

PCA9511, PCA9517, and PCA9548 follow the I2C specification (https://www.nxp.com/docs/en/user-guide/UM10204.pdf), which means that VIL max = 0.3VDD and VIH min = 0.7VDD.

Please check section 6 of the UM10204 I2C Specification for more detailed information.

Extra information:

PCA9511:

Once the connection circuitry is activated, the behavior of SDAIN and SDAOUT as well as SCLIN and SCLOUT become identical with each acting as a bidirectional buffer that isolates the input capacitance from the output bus capacitance while communicating the logic levels. A LOW forced on either SDAIN or SDAOUT will cause the other pin to be driven to a LOW by the part. The same is also true for the SCL pins

PCA9517:

When the A-side of the PCA9517 is pulled LOW by a driver on the I2C-bus, a comparator detects the falling edge when it goes below 0.3VCCA and causes the internal driver on the B-side to turn on, causing the B-side to pull down to about 0.5 V. When the B-side of the PCA9517 falls, first a CMOS hysteresis type input detects the falling edge and causes the internal driver on the A-side to turn on and pull the A-side pin down to ground.

Regards,

Jose

[Elaine_is]

Dear NXP Tech support,

I am confused at the VIL MAX of PCA9510 SCL/SDA.

The text lised below from PCA9510 datasheet page 6, it looks that the VIL max of PCA9510 SCL/SDA is 0.6V. No other detail VIL MAX description in datasheet.

PCA9510 is similar with device PCA9511, Can I refer to your reply and got that PCA9510 SCL/SDA follow the I2C specification (https://www.nxp.com/docs/en/user-guide/UM10204.pdf) VIL max=0.3VDD and VIH min = 0.7VDD.

PCA9510 datasheet page 6: 

8.3 Maximum number of devices in series
Each buffer adds about 0.1 V dynamic level offset at 25 °C with the offset larger at higher
temperatures. Maximum offset (Voffset) is 0.150 V with a 10 kΩ pull-up resistor. The LOW
level at the signal origination end (master) is dependent upon the load and the only
specification point is the I2C-bus specification of 3 mA will produce VOL < 0.4 V, although if
lightly loaded the VOL may be ~0.1 V. Assuming VOL = 0.1 V and Voffset = 0.1 V, the level
after four buffers would be 0.5 V, which is only about 0.1 V below the threshold of the
rising edge accelerator (about 0.6 V). With great care a system with four buffers may
work, but as the VOL moves up from 0.1 V, noise or bounces on the line will result in firing
the rising edge accelerator thus introducing false clock edges. Generally it is
recommended to limit the number of buffers in series to two, and to keep the load light to
minimize the offset.
The PCA9510A (rise time accelerator is permanently disabled) and the PCA9512A (rise
time accelerator can be turned off) are a little different with the rise time accelerator turned
off because the rise time accelerator will not pull the node up, but the same logic that turns
on the accelerator turns the pull-down off. If the VIL is above ~0.6 V and a rising edge is
detected, the pull-down will turn off and will not turn back on until a falling edge is
detected.