I2C Clock Stretching on MK10DX64VFM5

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I2C Clock Stretching on MK10DX64VFM5

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johnsotack
Contributor I

How can a slave force the I2C SCL line low for an adjustable time up to 5 ms?

A MK10DX64VFM5 is acting as an I2C.  It receives a command from the I2C master, followed by the master immediately reading the slave address for a response.  For some messages, the MK10DX64VFM5 slave needs additional time to form a response.  Clock stretching seems like an ideal solution but how to force SCL low and release it when desired is not clear from the manual.

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alejandrolozan1
NXP Employee
NXP Employee

Hi John,

Just like Héctor mentioned, it depends on the  I2Cx_C2 SBRC bit to 1 makes the slave baud rate independent.

You may want to try to control it by clearing the IICIF flag. Keeping IICIF flag uncleared in the slave isr keeps the clock held low, and when the IICIF is cleared the clock will be released.

Can you try that and let me know how it goes?

Regards,

Alejandro

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rev
Contributor III

I have a similar question to John.  I need a way to force SCL low when the I2C controller is configured as a slave.  This is a bit different than clock stretching, as I do not need (or want) to stretch every clock.

I tried Alejandro's suggestion to hold-off on clearing the IICIF flag.  However my observation is that SCL is released as soon as the I2C_D (data) register is read. 

I could wire up a GPIO to assert SCL low, but this seems like a hack.

Any other ideas on how to hold SCL for an extended period when in slave mode?

-- JAG

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hectorsanchez
Contributor IV

It depends on the SCL from the master.

Taking this info from the Reference Manual in chapter 40.4.1.7:

"The clock synchronization mechanism can be used by slaves to slow down the bit rate of

a transfer. After the master drives SCL low, a slave can drive SCL low for the required

period and then release it. If the slave's SCL low period is greater than the master's SCL

low period, the resulting SCL bus signal's low period is stretched. In other words, the

SCL bus signal's low period is increased to be the same length as the slave's SCL low

period."

Also you need to configure the I2Cx_C2 register the Slave Baud Rate Control (SBRC bit) so the slave baud rate follows the master baud rate.

You can find this register in the 40.3.6 section of the reference manual.

The link for the Reference Manual : http://cache.freescale.com/files/32bit/doc/ref_manual/K10P32M50SF0RM.pdf?fpsp=1

Hope this helps,

Hector Sanchez

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