I get both rising and falling flags on my CMP0 callback function (KL03Z)

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I get both rising and falling flags on my CMP0 callback function (KL03Z)

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filipdossche
Contributor III

Hi,

My application uses the CMP0 component.

When the callback function stops at the point where a rising edge is detected it invariably shows falling and rising flags simultaneously but there is at least 70 microseconds between the two events. (see screenshot).

pastedImage_0.png

I have enabled high hysteresis level and filtering but nothing helps. Any ideas or suggestions as to what may be wrong ?

More details:

I have added counters each time a rising or falling edge is detected: When I make it stop at the first rising edge the rising counter is correctly set to 1.

However, the falling counter is set to 7 or so. How can you get multiple falling edges (interrupts) without rising edges in between ?

I have worked out how to set up the KL03Z at 48 Mhz instead of the standard 8 Mhz which was used before hoping that might help but it makes no difference at all.

Message was edited by: Filip Dossche

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filipdossche
Contributor III

Dear XiangJun,

That is correct, it is a very sensible suggestion but whatever the quality of the incoming signal is or whether or not it oscillates I would expect to get both rising and falling interrupt flags.

In reality I more often than not got multiple falling edge interrupts without any rising edge ones.

The final solution is that, after setting everything up, use a flag and a delay of 10 ms to make things work as follows:

   1) Configure the CMP block.

   2) Set a flag to block full handling of incoming CMP interrupts.

   3) Activate CMP interrupts.

   4) Limited interrupt handling means a call to the same callback function but then it just clears the rising/falling flags.

   5) Wait for 10 ms.

   6) Then clear the limited interrupt handling flag.

Then everything works as expected: when I put a signal that goes from high to low and back again on the CMP unit's compare pin I get one recorded falling edge and one recorded rising edge.

I have not got the faintest idea why it freaks out just after setup but with the delay it works fine now.

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Dear Filip,

Regarding your question that both the rising and falling flags are set(CFR and CFF bits in CMPx_SCR) in ISR, I think it is dependent on the external input signals quality: INP and INM, if the two signals are all float, the CMP output signal will oscillate, in the case, both the CRF and CFF flags will be set. i do not know if it is your case.

For test purpose, you can use 6 bits DAC to generate a middle voltage for example 1.65V, and use an low speed clock signal as another input of CMP, then read the two flags, what is the result?

Hope it can help you.

BR

Xiangjun Rong

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filipdossche
Contributor III

Dear XiangJun,

That is correct, it is a very sensible suggestion but whatever the quality of the incoming signal is or whether or not it oscillates I would expect to get both rising and falling interrupt flags.

In reality I more often than not got multiple falling edge interrupts without any rising edge ones.

The final solution is that, after setting everything up, use a flag and a delay of 10 ms to make things work as follows:

   1) Configure the CMP block.

   2) Set a flag to block full handling of incoming CMP interrupts.

   3) Activate CMP interrupts.

   4) Limited interrupt handling means a call to the same callback function but then it just clears the rising/falling flags.

   5) Wait for 10 ms.

   6) Then clear the limited interrupt handling flag.

Then everything works as expected: when I put a signal that goes from high to low and back again on the CMP unit's compare pin I get one recorded falling edge and one recorded rising edge.

I have not got the faintest idea why it freaks out just after setup but with the delay it works fine now.

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