You can initialize the peripheral and then check the state of the pins, here is a common initialization:
void SPI0_mstrInit()
{
SIM_SCGC6 |= SIM_SCGC6_SPI0_MASK; //SPI0 Clock Gate enabled
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTC_MASK; //Port A Clock enabled
PORTA_PCR17 = PORT_PCR_MUX(0x02); //SPI0_SIN //with the TWR-K60N512 rev d B19
PORTA_PCR16 = PORT_PCR_MUX(0x02); //SPI0_SOUT //with the TWR-K60N512 rev d B20
PORTA_PCR15 = PORT_PCR_MUX(0x02); //SPI0_SCK //with the TWR-K60N512 rev d B15
PORTA_PCR14 = PORT_PCR_MUX(0x02); //SPI0_PCS0 //with the TWR-K60N512 rev d A16
SPI0_MCR = SPI_MCR_MSTR_MASK | //DSPI is in Master mode.
SPI_MCR_ROOE_MASK | //Incoming data is shifted into the shift register.
SPI_MCR_PCSIS(0x00) | //The inactive state of PCSx is high.
SPI_MCR_CLR_TXF_MASK | //Clear the TX FIFO counter.
SPI_MCR_CLR_RXF_MASK | //Clear the RX FIFO counter.
SPI_MCR_HALT_MASK; //Stop transfers
//SPI0_MCR |= SPI_MCR_DIS_TXF_MASK | //Tx FIFO is disabled.
// SPI_MCR_DIS_RXF_MASK; //Rx FIFO is disabled. ;
SPI0_SR |= SPI_SR_TCF_MASK | //Clear transfer complete flag
SPI_SR_EOQF_MASK | //Clear End of Queue Flag
SPI_SR_TFUF_MASK | //CLear Transmit FIFO Underflow Flag
SPI_SR_TFFF_MASK ; //Transmit FIFO Fill Flag
SPI0_CTAR0 |= SPI_CTAR_FMSZ(0x0F) | SPI_CTAR_PBR(0x3); //Frame Size = 15 + 1
//SPI0_RSER |= SPI_RSER_RFDF_RE_MASK | SPI_RSER_RFDF_DIRS_MASK | SPI_RSER_TFFF_DIRS_MASK; /* Set DMA Interrupt Request Select and Enable register */
SPI0_MCR &= ~SPI_MCR_HALT_MASK; //Start transfers.
}