How to use FIFO in uart comunication

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How to use FIFO in uart comunication

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IgorGonzalez
Contributor I

Hi,

I have already implement uart communication for modbus protocol and works well but now, I would like to implement with FIFOs.

I have some questions about it:

1.- How I have to enable FIFO feature for uart communication? It´s enough with the next code for the init uart configuration?

UART4_PFIFO |= (UART_PFIFO_TXFE_MASK | UART_PFIFO_TXFIFOSIZE(6));

2.- where I have to write my data? Is there any FIFO data register or I have to write UART4_D register? After modbus process, I have stored all my data in an array buffer and is it enough to send data to UART4_D or I have to take in account something else? Before to try to implements FIFOs, I used to check if TDRE was clear or not before send any other byte.

if(b8envia_mensaje_modbus == TRUE_B1) {

     for (u8nn = CERO_U8; u8nn < u8sendCounter; u8nn++){

          //while((UART4_S1&UART_S1_TDRE_MASK)==0) {}

          UART4_D = aru8sendBuf[u8nn];

     }

}

3.- Last question is about how can I control uart4 isr to clear a own flag to know that all data has been sent. I´m not sure if S1[TDRE] flag is set when TXFIFO gets empty or equal to TXWATER value.

    if ((UART_S1_REG(UART4_BASE_PTR) & UART_S1_TDRE_MASK) == UART_S1_TDRE_MASK){

             UART4_S1;//clear isr

             b8envia_mensaje_modbus = FALSE_B1;//own flag

             GPIOC_PCOR |= 0x00002000; //clear manual CTS

             GPIOC_PCOR |= 0x00001000; //clear manual RTS

           }

Thanks in advance

Igor Gonzalez

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alejandrolozan1
NXP Employee
NXP Employee

Sorry for the delay. In case you still need the below information:

1.- How I have to enable FIFO feature for uart communication? It´s enough with the next code for the init uart configuration?

You have to enable the FIFO in the next way:

/* Enable the FIFOs */

    UART_PFIFO_REG(tx_module) |= UART_PFIFO_TXFE_MASK;

    UART_PFIFO_REG(rx_module) |= UART_PFIFO_RXFE_MASK;

But the FIFO size cannot be modified, you can modify the watermark. For example:

/* Test all possible values for the watermarks */

    for( i=1; i < 8; i++)

    {   

        /* Set the Tx watermark */

        UART_TWFIFO_REG(tx_module) = i;

2.- where I have to write my data? Is there any FIFO data register or I have to write UART4_D register? After modbus process, I have stored all my data in an array buffer and is it enough to send data to UART4_D or I have to take in account something else? Before to try to implements FIFOs, I used to check if TDRE was clear or not before send any other byte.

if(b8envia_mensaje_modbus == TRUE_B1) {

     for (u8nn = CERO_U8; u8nn < u8sendCounter; u8nn++){

          //while((UART4_S1&UART_S1_TDRE_MASK)==0) {}

          UART4_D = aru8sendBuf[u8nn];

     }

}


That is correct, you have to use the UARTx_D resgister.

3.- Last question is about how can I control uart4 isr to clear a own flag to know that all data has been sent. I´m not sure if S1[TDRE] flag is set when TXFIFO gets empty or equal to TXWATER value.

    if ((UART_S1_REG(UART4_BASE_PTR) & UART_S1_TDRE_MASK) == UART_S1_TDRE_MASK){

             UART4_S1;//clear isr

             b8envia_mensaje_modbus = FALSE_B1;//own flag

             GPIOC_PCOR |= 0x00002000; //clear manual CTS

             GPIOC_PCOR |= 0x00001000; //clear manual RTS

           }

From the RM:

For more efficient interrupt servicing all data except the final value to be written to the buffer

should written to D/C3[T8]. Then S1 can be read before writing the final data value, resulting in the

clearing of the TRDE flag. This is more efficient since the TDRE will reassert until the watermark has been

exceeded so attempting to clear the TDRE every write will be ineffective until sufficient data has been

written.

View solution in original post

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1 Reply
583 Views
alejandrolozan1
NXP Employee
NXP Employee

Sorry for the delay. In case you still need the below information:

1.- How I have to enable FIFO feature for uart communication? It´s enough with the next code for the init uart configuration?

You have to enable the FIFO in the next way:

/* Enable the FIFOs */

    UART_PFIFO_REG(tx_module) |= UART_PFIFO_TXFE_MASK;

    UART_PFIFO_REG(rx_module) |= UART_PFIFO_RXFE_MASK;

But the FIFO size cannot be modified, you can modify the watermark. For example:

/* Test all possible values for the watermarks */

    for( i=1; i < 8; i++)

    {   

        /* Set the Tx watermark */

        UART_TWFIFO_REG(tx_module) = i;

2.- where I have to write my data? Is there any FIFO data register or I have to write UART4_D register? After modbus process, I have stored all my data in an array buffer and is it enough to send data to UART4_D or I have to take in account something else? Before to try to implements FIFOs, I used to check if TDRE was clear or not before send any other byte.

if(b8envia_mensaje_modbus == TRUE_B1) {

     for (u8nn = CERO_U8; u8nn < u8sendCounter; u8nn++){

          //while((UART4_S1&UART_S1_TDRE_MASK)==0) {}

          UART4_D = aru8sendBuf[u8nn];

     }

}


That is correct, you have to use the UARTx_D resgister.

3.- Last question is about how can I control uart4 isr to clear a own flag to know that all data has been sent. I´m not sure if S1[TDRE] flag is set when TXFIFO gets empty or equal to TXWATER value.

    if ((UART_S1_REG(UART4_BASE_PTR) & UART_S1_TDRE_MASK) == UART_S1_TDRE_MASK){

             UART4_S1;//clear isr

             b8envia_mensaje_modbus = FALSE_B1;//own flag

             GPIOC_PCOR |= 0x00002000; //clear manual CTS

             GPIOC_PCOR |= 0x00001000; //clear manual RTS

           }

From the RM:

For more efficient interrupt servicing all data except the final value to be written to the buffer

should written to D/C3[T8]. Then S1 can be read before writing the final data value, resulting in the

clearing of the TRDE flag. This is more efficient since the TDRE will reassert until the watermark has been

exceeded so attempting to clear the TDRE every write will be ineffective until sufficient data has been

written.

View solution in original post

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