Zoran
The defines from kinetis.h at the link are:
#define CORTEX_M4_BLOCK 0xe000e000
#define RAM_START_ADDRESS (0x20000000 - (SIZE_OF_RAM/2)), where SIZE_OF_RAM is (128 * 1024) for the FRDM_K22
#define SYSTICK_PRIORITY 7 (mid-value - but can be chosen to be 0..15 of Cortex M4)
#define __interrupt (dummy define)
VECTOR_TABLE is
typedef struct stVECTOR_TABLE
{
RESET_VECTOR reset_vect;
void (*ptrNMI)(void);
void (*ptrHardFault)(void);
void (*ptrMemManagement)(void);
void (*ptrBusFault)(void);
void (*ptrUsageFault)(void);
unsigned long ptrReserved0;
unsigned long ptrReserved1;
unsigned long ptrReserved2;
unsigned long ptrReserved3;
void (*ptrSVCall)(void);
void (*ptrDebugMonitor)(void);
unsigned long ptrReserved4;
void (*ptrPendSV)(void);
void (*ptrSysTick)(void);
//PROCESSOR_IRQ processor_interrupts; // length is processor specific
} VECTOR_TABLE;
where RESET_VECTOR is
typedef struct stRESET_VECTOR
{
void *ptrResetSP; // initial stack pointer
void (*ptrResetPC)(void); // initial program counter
} RESET_VECTOR;
You need to add the following line of code to allow the interrpt vector table to be in SRAM:
VECTOR_TABLE_OFFSET_REG = (unsigned long *)(RAM_START_ADDRESS);
which is defined as
| #define VECTOR_TABLE_OFFSET_REG | *(unsigned long *)(CORTEX_M4_BLOCK + 0xd08) // Interrupt Control State Register |
| #define TBLBASE_IN_RAM | 0x20000000 // vector table base is in RAM |
| #define TBLBASE_IN_CODE | 0x00000000 |
| #define TBLOFF_MASK | 0x1fffff80 // table offset from bottom of Code / RAM |
You may need to globally enable interrupts with something like:
__asm__("cpsie i"); (when using KDS)
or
__enable_irq(); (when using Keil).
Also you should put a prototype for RealTimeInterrupt() at the start of the file.
Finally you need to ensure that there are no variables located at the start of SRAM by starting the variables in the linker script file at
0x1fff01f0 rather than 0x1fff0000
eg. (for KDS)
SECTIONS
{
__SRAM_segment_start__ = 0x1fff01f0;
__SRAM_segment_end__ = 0x2000ffff;
...
With these mods you may get it to build and run - then you can turn your attention back to the original question about the core clock speed.
Regards
Mark