Hi
You can get some more real-word advice on the clocking at http://www.utasker.com/kinetis/MCG.html
For the KL03 you can clock directly from the IRC48M for 48MHz or from the LIRC for 2MHz or 8MHz.
If you were to use the uTasker project these are the settings to choose all options (with 48MHz valid):
#define RUN_FROM_HIRC // clock from internal 48MHz RC clock
//#define RUN_FROM_LIRC // clock from internal 8MHz/2MHz RC clock
#if defined RUN_FROM_HIRC
#define SYSTEM_CLOCK_DIVIDE 1 // 1..16
#define BUS_CLOCK_DIVIDE 2 // 1..8 (valid for bus/flash and divisor is after the system clock divider)
#elif defined RUN_FROM_LIRC
#define RUN_FROM_LIRC_2M // selet 2MHz rather than 8MHz
#define SLOW_CLOCK_DIVIDE 1 // optionally divide the slow clock output (1, 2, 4, 8, 16, 32, 64 or 128)
#define SYSTEM_CLOCK_DIVIDE 1 // 1..16
#define BUS_CLOCK_DIVIDE 2 // 1..8 (valid for bus/flash and divisor is after the system clock divider)
#else // run from the 32kHz osciallator
#define SYSTEM_CLOCK_DIVIDE 1 // 32kHz
#define BUS_CLOCK_DIVIDE 1 // 32kHz
#endif
The actual code that configures the 48Mhz case is:
//MCG_MC = MCG_MC_HIRCEN; // this is optional and would allow the HIRC to run even when the processor is not working in HIRC mode
MCG_C1 = MCG_C1_CLKS_HIRC; // select HIRC clock source
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_HICR) { // wait until the source is selected
}
SIM_CLKDIV1 = (((SYSTEM_CLOCK_DIVIDE - 1) << 28) | ((BUS_CLOCK_DIVIDE - 1) << 16)); // prepare bus clock dividesBelow is the uTasker KL03 simulator confirming the clock speeds obtained:
Regards
Mark
Kinetis for professionals: http://www.utasker.com/kinetis.html
Hi
You can get some more real-word advice on the clocking at http://www.utasker.com/kinetis/MCG.html
For the KL03 you can clock directly from the IRC48M for 48MHz or from the LIRC for 2MHz or 8MHz.
If you were to use the uTasker project these are the settings to choose all options (with 48MHz valid):
#define RUN_FROM_HIRC // clock from internal 48MHz RC clock
//#define RUN_FROM_LIRC // clock from internal 8MHz/2MHz RC clock
#if defined RUN_FROM_HIRC
#define SYSTEM_CLOCK_DIVIDE 1 // 1..16
#define BUS_CLOCK_DIVIDE 2 // 1..8 (valid for bus/flash and divisor is after the system clock divider)
#elif defined RUN_FROM_LIRC
#define RUN_FROM_LIRC_2M // selet 2MHz rather than 8MHz
#define SLOW_CLOCK_DIVIDE 1 // optionally divide the slow clock output (1, 2, 4, 8, 16, 32, 64 or 128)
#define SYSTEM_CLOCK_DIVIDE 1 // 1..16
#define BUS_CLOCK_DIVIDE 2 // 1..8 (valid for bus/flash and divisor is after the system clock divider)
#else // run from the 32kHz osciallator
#define SYSTEM_CLOCK_DIVIDE 1 // 32kHz
#define BUS_CLOCK_DIVIDE 1 // 32kHz
#endif
The actual code that configures the 48Mhz case is:
//MCG_MC = MCG_MC_HIRCEN; // this is optional and would allow the HIRC to run even when the processor is not working in HIRC mode
MCG_C1 = MCG_C1_CLKS_HIRC; // select HIRC clock source
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_HICR) { // wait until the source is selected
}
SIM_CLKDIV1 = (((SYSTEM_CLOCK_DIVIDE - 1) << 28) | ((BUS_CLOCK_DIVIDE - 1) << 16)); // prepare bus clock dividesBelow is the uTasker KL03 simulator confirming the clock speeds obtained:
Regards
Mark
Kinetis for professionals: http://www.utasker.com/kinetis.html
