One thing to note about the CMSIS API is that it doesn't make it 'obvious' what the 'range' of priority values needs to be. You will find that for these M0-core devices you have 0,1,2 and 3 to work with -- lower numbers, higher priority. That is, the API 'shifts' the supplied priority into the available 'upper bits' of the NVIC architecture:
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));