How to decrease ADC sampling / conversion time ?

[mohammedaboelna]

Hello,

I am working on target KEAZN64 trying to configure the ADC peripheral using FIFO mode.

I need to decrease the ADC sampling/conversion time as my constraint is to return the results of the FIFO buffer before 100 microseconds from triggering the buffer.

I.e. Time between triggering FIFO buffer for sampling and getting true values for the channels should not exceed 100 microseconds.

I found out in the datasheet these timings.

Conversion time = ( 23 ADCK Cyc / 8 MHz ) + (5 Busclk cycles / 8).

In this example, Bus clock = 8 MHz.

At my side, Bus clock = 16 MHz. and I configured ADCK to work by 8 MHz.

By 8 MHz, All ADC channels of the FIFO buffer are working good and can return true values correctly.

However; when I configured the ADCK to work by the bus clock (16 MHz) directly to meet my constraint (100 us total time), ADC channels can not convert correctly and driver is not working good.

My questions are:

1) why the 16 MHz can not let the ADC driver to convert correctly.

     Is it limited to the hardware components inside or outside at the sensor side ?

2) Are there any general proposals to decrease ADC sampling/conversion time for FIFO  channels please ?

Thank you in advance.

[Robin_Shen]

1. The ADC conversion clock frequency(fADCK) should not exceed 8MHz. You can find it in "Table 11. 5 V 12-bit ADC operating conditions" of S9KEA64P64M20SF0.

2. Have you try to use the interrupt mode? Please refer the "24.5.2 ADC FIFO module initialization example" of S9KEA64Z64M20SF0RM.

Best Regards,

Robin

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