Hi Laartoor,
According to the information provided by ARM the Cortex-M4 which is the one that the K60 Family has support both level-sensitive and pulse interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Tipically this happens because the ISR (Interrupt Service Routine) accesses the peripheral, causing it to clear the interrupt request. If the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. This means that the peripheral can hold the interrupt signal asserted until it no longer requires servicing.
The normal way to works is that the system will have some interrupt controller external to the ARM core, in this case the K60 device, which takes the interrupt sources and drives the IRQ pin. The interrupt service routine would then read a memory mapped register in the interrupt controller hardware (a K60 module), to find out which interrupt source was active.
All the interrupts in the Kinetis devices are handled as level-sensitive as you can see in all the peripheral which support an interrupt option; they have a register to erase the interrupt flag.
I hope this information solve your queries.
Regards,
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