How is the NVIC wired up?

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How is the NVIC wired up?

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Laartoor
Contributor III

I wonder how the peripheral interrupt inputs are connected to the Kinetis processors, especially the Kx0 series. According to the ARM documentation, there are two possibilities: as level sensitive, or as pulse sensitive. I could not find anything about this in the Kinetis documentation, so could someone help me out?

As the peripherals all have their own interrupt flags, which can be cleared independently from the NVIC, I strongly suspect that Freescale has chosen a level-sensitive implementation. There are subtle differences in behavior between the two with regards to when an interrupt becomes pending, and in order to avoid surprises, it would be very helpful to know which implementation was selected for each peripheral.

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adriancano
NXP Employee
NXP Employee

Hi Laartoor,

According to the information provided by ARM  the Cortex-M4 which is the one that the K60 Family has support both level-sensitive and pulse interrupts.

A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Tipically this happens because the ISR (Interrupt Service Routine) accesses the peripheral, causing it to clear the interrupt request. If the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. This means that the peripheral can hold the interrupt signal asserted until it no longer requires servicing.

The normal way to works is that the system will have some interrupt controller external to the ARM core, in this case the K60 device, which takes the interrupt sources and drives the IRQ pin. The interrupt service routine would then read a memory mapped register in the interrupt controller hardware (a K60 module), to find out which interrupt source was active.

All the interrupts in the Kinetis devices are handled as level-sensitive as you can see in all the peripheral which support an interrupt option; they have a register to erase the interrupt flag.

I hope this information solve your queries.

Regards,

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adriancano
NXP Employee
NXP Employee

Hi Laartoor,

According to the information provided by ARM  the Cortex-M4 which is the one that the K60 Family has support both level-sensitive and pulse interrupts.

A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Tipically this happens because the ISR (Interrupt Service Routine) accesses the peripheral, causing it to clear the interrupt request. If the signal is not deasserted before the processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR again. This means that the peripheral can hold the interrupt signal asserted until it no longer requires servicing.

The normal way to works is that the system will have some interrupt controller external to the ARM core, in this case the K60 device, which takes the interrupt sources and drives the IRQ pin. The interrupt service routine would then read a memory mapped register in the interrupt controller hardware (a K60 module), to find out which interrupt source was active.

All the interrupts in the Kinetis devices are handled as level-sensitive as you can see in all the peripheral which support an interrupt option; they have a register to erase the interrupt flag.

I hope this information solve your queries.

Regards,

-----------------------------------------------------------------------------------------------------------------------

Note: If this post answers your question, please click the Correct Answer button. It would be nice!

-----------------------------------------------------------------------------------------------------------------------

View solution in original post

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