Clive
I use this code to bit bang to EZPORT of other devices. There is no difference between K and KL GPIO port code.
- The ports need first to be configured as inputs or outputs before use.
- the clock phase matches the EZPORT so may need to be adjusted for certain SPI slaves
- port used and ports bits may need to be changed to suit
- whether setup and hold delays are required depends on your CPU speed and the SPI slave's speed. I needed 1us delays for the EZPORT to work when using the code on 100MHz devices because the GPIOx_PSOR and GPIOx_PCOR operations are pretty fast.
| #define EZRESETOUT | PORTD_BIT15 | // port output for reset signal |
| #define EZCSOUT | PORTD_BIT11 | // SPI2_SC0 |
| #define EZDIN | PORTD_BIT13 | // SPI2_MOSI |
| #define EZDOUT | PORTD_BIT13 | // SPI2_MISO |
| #define EZCLKOUT | PORTD_BIT12 | // SPI2_CLK |
// Send and receive a single byte
//
static unsigned char fnSendEZPORT(unsigned char ucDataOut)
{
| unsigned char ucBit = 0x80; | // data sent and receive most significant bit first |
| unsigned char ucReadByte = 0; |
| do { |
| | GPIOD_PSOR = EZCLKOUT; | // generate rising clock edge |
| | fnDelayLoop(1); |
| | if (ucDataOut & ucBit) { | // set new data output state |
| | GPIOD_PSOR = EZDOUT; |
| | } |
| | else { |
| | GPIOD_PCOR = EZDOUT; |
| | } |
| | fnDelayLoop(1); |
| | GPIOD_PCOR = = EZCLKOUT; | // falling clock edge |
| | fnDelayLoop(1); | |
| | GPIOD_PSOR = EZCLKOUT; | // rising clock edge |
| | if (GPIOD_PDIR & EZDIN) { | // read data in |
| | ucReadByte |= ucBit; |
| | } |
| | ucBit >>= 1; |
| } while (ucBit != 0); |
| return ucReadByte; |
}
Regards
Mark
