FlexCAN Message Buffer Clarification

[benjaminschroed]

I've been researching how to utilize the FlexCAN interface for the MK61FX512VMJ15, and need some clarification about about how many message buffers are actually supported.

With the documentation going back and forth on using the terminology "message buffer", "mailbox" and "MB", it has become very difficult to understand the reference manual.

I don't plan on using the RxFIFO.  I plan on configuring buffers to be specific to a certain ID mask.  How many of these buffers can I enable?  Is it only 16, or are there more available if I disable RxFIFO?  I have a need to support around 50 unique IDs.  Now, they come at regular intervals, so I could dynamically change the mask, but this is less than ideal.

Can anyone provide any insight?

Thanks!

[sywksmstkadlfgk]

You will need to set up the mailbox filters so multiple message IDs come into a single mailbox. You will need to then filter again when you pull the message out of the mailbox. Think of the message box filter as a course filter that reduces the final filtering/sorting workload.

[benjaminschroed]

Thanks for the comments.  The method I chose to use was to just have all 16 mailboxes able to receive anything with no masking, and I periodically check them.  I got all caught up into thinking I needed masking, but just queuing the messages is sufficient.

Thanks again!

[egoodii]

Its not clear why you discount the RxFIFO mode.  It takes-over the first 8 MBs, and queues up to six messages in received order for you, giving you just 'one place' to look for them.  You can use the remaining 8 MBs as a combination of TX mailboxes and/or up to 40 RX filters to apply to messages to go into the FIFO (not useful, of course, if you are resigned to just take 'em all in like I do for J1939).

[benjaminschroed]

I think the reason is that I realized masking is not important to me since I will just poll and look to see what I have periodically.  With that being the case, a FIFO would make sense, but it sounds like to me I could only have 8 FIFO + 8 Mailboxes, and at this point, I might as well make them all Mailboxes just to make it easy and consistent.  If I could go 16 deep in FIFO mode, that would be good, but the masking has no value for me, so I just treat the mailboxes as a pseudo-FIFO with how I poll them.  I might be receiving more than 8 messages (but less than 16) in between my polling times.

[egoodii]

The actual FIFO depth is only 6 (for some reason, even though it 'takes over' 8MBs...), so if you need the hardware to buffer 'more than 8' between potential times-to-process, then by all means your MB plan is necessary.  Note that IF 'sequence of reception' becomes important (say as part of a longer Segmentation-and-Reassembly group) you may have to pay attention to the timestamps in each MB to 'process them in actual order'.

If all 16 MBs are dedicated to RX, I take it there is NO TX activity in this device.

[ndavies · Accepted solution]

You won't be able to have an individual mailbox for each message. There's not enough mailboxes. You'll miss messages if you continually reprogram mail box message filters. CAN messages can be held up indefinitely if they are a low enough priority and the bus bandwidth usage is high. Changing ID filters won't work due to CANs priority arbitration. You can't guaranty the timing or order of the messages.

You will need to set up the mailbox filters so multiple message IDs come into a single mailbox. You will need to then filter again when you pull the message out of the mailbox. Think of the message box filter as a course filter that reduces the final filtering/sorting workload.

Norm

[xiangjunrong]

Hi,Benjamin,

I have to admit that the FlexCan chapter is unclear. Regarding your question, the "message buffer", "mailbox" and "MB" are the same concept. Regarding the total  number of MB, pls refer to section 53.3.1 FlexCAN Memory Mapping in the RM of K61 at page 1622, there are total 16 MBs which can be used as receiver MB or transmitter MB but not both at the same time. I copy it here. The address of MB is from 0x4002_4080 to 0x4002_417F, the address of MB0 is from 0x4002_4080 to 0x4002_408F.

Because you receive 50 individual ID, if you do not use receiver FIFO, you have to use mask function so that some bits of ID are "DO NOT care" , you can receive more IDs. In your case, you can use receiver FIFO mode as NORM Davies pointed out, for example, the MB0~MB5 can be receiver FIFO, the remaining MB can be transmitter MBs, it is okay, in FIFO mode, you can write multiple accepted receiver ID.

Hope it can help you

BR

Xiangjun Rong

This module's memory map includes sixteen 128-bit message buffers (MBs) that occupy

the range from offset 0x80 to 0x17F.