FRDM-KL27Z Schematics and Bootloader Questions

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FRDM-KL27Z Schematics and Bootloader Questions

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adamgarrison
Contributor III

I'm doing a fairly simple design using the MKL17Z256VFM4.

There's a couple of things I'd like to ask you.

I ordered the FRDM-KL27Z as a dev platform.

Is this the best dev platform for the KL17?

Are the schematics available? I didn't find them.

About the ROM Bootloader:

Apparently you can force the CPU to enter the bootloader by asserting the BOOTCFG0 pin which is apparently the NMI_b pin; what does assert mean in this case? Is it high or low?

  The Bootloader looks at LPUART among others as a boot device. Which one does it use? LPUART0 or LPUART1 or both?

Thanks for your help,

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Rick_Li
NXP Employee
NXP Employee

Hi Adam,

Yes, FRDM-KL27 is the best dev platform for KL17 at present.

Compare, FRDM-KL27 only has one USB module than KL17.

The schematic is attached here. It is still not available at Freescale website.

Regarding Bootloader:

BOOTCFG0 pin need in low level to enter bootloader when power on.

It use LPUART0 as the boot device.

hope it helps!

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Rick_Li
NXP Employee
NXP Employee

Hi Adam,

Yes, FRDM-KL27 is the best dev platform for KL17 at present.

Compare, FRDM-KL27 only has one USB module than KL17.

The schematic is attached here. It is still not available at Freescale website.

Regarding Bootloader:

BOOTCFG0 pin need in low level to enter bootloader when power on.

It use LPUART0 as the boot device.

hope it helps!

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adamgarrison
Contributor III

Hi Yong Li,

Thank you for the input and the schematics.

In my research I was unable to find where only LPUART0 is the boot device.  Section 13.4.3 of the K27 TRM does not mention that the Boot device is restricted to LPUART0.  Can you please direct me to where this assignment to only LPUART0 is mentioned in the TRM?

Also, in the case of the MKL17Z256VFM4 (32 QFN) the LPUART0 two locations in the pinmap.

For example LPUART0_RX can be on pin 11 or 31, likewise LPUART0_TX can be on pin 12 or 32.

Am I obliged to use a particular RX/TX pair or does the ROM bootloader check both?

Thank you,

Adam

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dmarks_ls
Senior Contributor I

Adam Garrison wrote:

In my research I was unable to find where only LPUART0 is the boot device.  Section 13.4.3 of the K27 TRM does not mention that the Boot device is restricted to LPUART0.  Can you please direct me to where this assignment to only LPUART0 is mentioned in the TRM?

Also, in the case of the MKL17Z256VFM4 (32 QFN) the LPUART0 two locations in the pinmap.

For example LPUART0_RX can be on pin 11 or 31, likewise LPUART0_TX can be on pin 12 or 32.

Am I obliged to use a particular RX/TX pair or does the ROM bootloader check both?

I second this query.  I'm looking at the reference manual for the KL17 (KL17P64M48SF6RM.pdf), and one would be hard-pressed to say definitively which SPI, I2C, and LPUART pins are active within the bootloader.  In fact, there would seem to be conflicting information.  From page 185, section 13.2.9, Bootloader Exit State, detailing which registers and peripherals are not returned to their default state after a bootloader operation:

Affected pin mux:

• UART1(PTE0, PTE1)

• I2C1(PTC10, PTC11)

• SPI1(PTD4, PTD5, PTD6, PTD7)

But this is from page 190, section 13.3.3, LPUART Peripheral:

Autobaud feature: If LPUARTn is used to connect to the bootloader, then the LPUARTn_RX (PTA1) pin must be kept high and not left floating during the detection phase in order to comply with the autobaud detection algorithm.

So, Freescale, which is it?  I'm pretty sure from other forum posts I've read that it's LPUART0 on PTA1/2 that's used for the bootloader.  And if someone wanted to use I2C to bootload the device, can we be sure it's PTC10/11?  Those pins aren't even available on the 32-pin and 48-pin parts, only the 64-pin package.  It would be extremely useful if you would update your documentation and make it clear which communication pins are active for a given Kinetis device in the bootloader.

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Jorge_Gonzalez
NXP Employee
NXP Employee

Hello David Rodgers:

Sorry for the confusion caused. The technical documentation team is working on updating the manuals.

The correct pinout should be this:

Pinmux
PortSignal   Alt
PTA1LPUART0_RX  ALT2
PTA2LPUART0_TX    ALT2
PTB0I2C0_SCL  ALT2
PTB1I2C0_SDA  ALT2
PTC4SPI0_PCS0  ALT2
PTC5SPI0_SCK  ALT2
PTC6SPI0_MOSI  ALT2
PTC7SPI0_MISO  ALT2

Regards!

Jorge Gonzalez

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