FRDM K64F Clock Setup

[teixi]

Hello everybody,

I am working in some DSP experiments with the FRDM K64F (MK64FN1M0VLL12) and programing with Keil uVision5 I am not able to make the CPU work at full speed (120MHZ).

I am using the Pack Installer on Keil to add the startup and system files to the project.

By default the FRDM K64F Core clock is set to 41.94Mhz inside the system_MK64F12.c files. ( Keil add the version 1.0, 2013-08-12 of this file) and everything works correctly. However if I change the CLOCL_SETUP to 3 the program get stack during the initialization at the following point:

  while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */

  }

Some one have had the same problem? Anyone have an example of the FRDM K64F working at 120Mhz on Keil? There is an other version of the system_MK64F12.c?

Thanks in advance.

** ###################################################################

*/

/*!

* @file MK64F12

* @version 1.0

* @date 2013-08-12

* @brief Device specific configuration file for MK64F12 (implementation file)

*

* Provides a system configuration function and a global variable that contains

* the system frequency. It configures the device and initializes the oscillator

* (PLL) that is part of the microcontroller device.

*/

#include <stdint.h>

#include "MK64F12.h"

#define DISABLE_WDOG    1

#define CLOCK_SETUP     3

/* Predefined clock setups

   0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode

         Reference clock source for MCG module is the slow internal clock source 32.768kHz

         Core clock = 41.94MHz, BusClock = 41.94MHz

   1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode

         Reference clock source for MCG module is an external crystal 8MHz

         Core clock = 100MHz, BusClock = 50MHz

   2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode

         Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication

         Core clock = 8MHz, BusClock = 8MHz

   3 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode

         Reference clock source for MCG module is an external crystal 8MHz

         Core clock = 120MHz, BusClock = 60MHz

*/

[teixi · Accepted solution]

Thanks for your answer John, It was very useful.

Finally I found the solution. I post it here in case someone have the same problem.

The files included by Keil for the FRDM K64F are an initial version and have some bugs. Hopefully Keil will  update the package for this platform soon but until then the solution is to change some files manually.

The files that need to be changed (version 2.5) are :

- MK64F12.h

- system_MK64F12.h

- system_MK64F12.c ( you need to delete some includes on this file and include instead the file MK64F12.h)

You don't need to change the files startup_MK64F12.s. With the version 1.0 it works fine.

Where to find the updated version of this files? There is a software package called Kinetis SDK 1.0.0 that can be downloaded from www.freescale.com/ksdk and include this files.

Regards :smileyhappy:,

Joan

[johnbaker]

Hi Joan,

I have also been doing some benchmarks between CodeWarrior and KDS.  KDS knocked the socks off of CodeWarrior and the only thing I can attribute it to is this attached started file that runs before my main.c code.

Take a look at it.  It may help you out.

John Baker

AVG

[BlackNight]

not for Keil, but this might help you:

http://mcuoneclipse.com/2014/06/14/frdm-k64f-atmaximum-speed-of-120-mhz/

Erich

[BlackNight]

just in case: attached such a project for 120 MHz core and 60 MHz bus (for Eclipse/GNU).

Erich

[BlackNight]

ups, missed to attach the file.

Project is on GitHub:

mcuoneclipse/Examples/Eclipse/FRDM-K64F/FRDM-K64F_BlinkLED at master · GitHub

Erich

[teixi]

Thanks Erich, very useful material. I will work on it today and I will let you know my results.