DMA for I2S

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DMA for I2S

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Mohsin455
Contributor IV

Hi,

 

         I want to use DMA for Tx/Rx I2S data to/from codec and was wondering if the following will work.

 

 - Set the I2S RX DMA at priority 15 to Receive data from codec 

 - Set the I2S TX DMA at priority 14 to Transmit data to codec

 

Since the Rx DMA (wth higher priority of 15 ) will always be on, will it allow the Tx DMA to run ?

 

 

Thanks,

Mohsin455

 

 

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egoodii
Senior Contributor III

You don't say how many channels you will run, or how you want to see the audio structures in memory, but see this link for a DMA setup that directly de-interleaves the CoDec channel data into (and out of) linear ping-pong buffers for each channel, all using one DMA control register set: https://community.freescale.com/message/82190#82190

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Mohsin455
Contributor IV

Hi Egoodii,

 

                      Thanks for your reply. I am using it is I2S format with stereo (left and right). I want to know the following from your code

 

1) Why do we need DMA_CSR_BWC(3) ?

 

2)  My setup is similar to yours but the only difference is I am using it for I2S mode and also, I am setting the interrupt to occurs after the major count is completed and then reseting the address in the ISR. What I am wondering is while the Rx has got higher priority it will not allow the Tx  because the Rx DMA should be running continuously?

 

3) Another issues is with I2S in stereo mode. What I am not sure after reading the manual is how do we connect I2S0_TX0 and I2S0_TX1 (since stereo) to single I2S_DMA channel ?

 

Thanks,

Mohsin

 

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egoodii
Senior Contributor III

1 -- Bandwidth control to 'slowest' just on general principles.  Even with my six channels each way, I have no need to allow DMA to 'hog' memory access to fill or empty a FIFO.

2 -- I don't know what your overall sample rate is, but I CERTAINLY wouldn't want to count on interrupt response time throughout a whole complex system to insure access to DMA address controls between the end of one sample set and the start of the next.  That's why I set my major cycle to 'rewind' itself, AND to interrupt at both 'half' and 'full' points, so that my memory arrays are complete double-buffer (ping-pong) sets I can be absolutely assured are aligned, contiguous data points as long as my overall interrupt/processing-overhead completes in less than one sample-set time (one half of overall buffer size in sample counts).  I don't think we can worry about 'DMA priority' especially -- you say 'running continuously', but even if you run some exotic 128Ksamples/s the DMA is still 'idle' in each direction 99% of the time.  Once the RX FIFO is empty, that DMA channel will stall until more show up.

3 -- My setup is 'network' mode to allow many channels, you want only two.  I think we can assume I2S (normal stereo mode) is a configurable subset in terms of data controls thru DMA.  You mention TX0 and TX1 (and I assume RX0 and RX1) FIFO usage, as in 'two channel operation' TCHEN.  I don't think you can, or want to, DMA that way -- you've only got one-each TX and RX DMA requests, and this would force the DMA to shuttle back and forth between the two FIFO registers, for no particular advantage.  With DMA you probably don't need FIFOs at all.

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Mohsin455
Contributor IV

Hi Egoodii,

 

                            Thanks for your reply. I am running at 48K and hence much slower compared to your setup.

 

I was a bit confused from looking at the documentation on weather the higher priority DMA 's are always active or not.

 

Also on I2S TCHEN, I was thinking if I am missing anything. But as you say with DMA we cannot use this feature. 

 

Thanks,

Mohsin

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Mohsin455
Contributor IV

Hi Egoodii,

 

                       I am not getting the half complete interrupt. Also found the following "If BITER is set, do not use INTHALF. Use INTMAJOR instead"

 

What does "BITER is set" means ?

 

Also can you confirm if you are getting the interrupts at half point ?

 

Thanks,

Mohsin

 

 

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Mohsin455
Contributor IV

Hi Egoodii,

 

                   I don't think we can set the half/full interrupt at the same time.

 

Regards,

Mohsin

 

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Mohsin455
Contributor IV

Hi All,

 

            Can anyone please confirm if we can use half/full interrupt at the same time ?

 

Thanks,

Mohsin455

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egoodii
Senior Contributor III

Back in my code referenced earlier, I do indeed enable the 'half' interrupt, and the 'major loop' interrupt, and between the two I get an interrupt on each half-buffer-usage so that my linear buffers do result in full ping-pong operations:

DMA_CSR(RX_DMA_Chan)            = DMA_CSR_BWC(3) | DMA_CSR_INTHALF_MASK | DMA_CSR_INTMAJOR_MASK;

 

--ERGII

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Mohsin455
Contributor IV

 

Yes, but the document says the following

 

"If BITER is set, do not use INTHALF. Use INTMAJOR instead"

 

and I was not getting the half complete interrupt when I enabled both.

 

Regards,

Mohsin455

 

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egoodii
Senior Contributor III

I can't say anything about that particular statement in the documentation; the Block ITERation count certainly has to be 'set' to 'something' for all users, AFAIK.  Certainly for some uses of major/minor cycles 'IntHalf' makes no sense.  All I can tell you is the exact DMA setup I linked to earlier is working very well for us, doing all the interleaved ping-pong double-buffering (for six channels in our case!) to/from Ethernet and three TLV320AIC3104 CoDecs, 16bit, all at 32K/s/channel.  I think the 'defines' allow that DMA setup to be easily ported to any reasonable number of channels-in-use.

 

You haven't detailed any of what you are setting into DMA controls (such as CITER and BITER), and very little about what you are trying to accomplish overall, so my ability to comment is limited.

 

One caveat I will note -- this DMA-from-I2S operation is NOT particularly tolerant of 'suspension', such as due to debugger operations, and I am not aware of any reasonable means to make it 'self healing' when it does get out-of-sync.

 

--ERGII