DDR troubleshooting tips?

[alipoth]

I am trying bring up a LPDDR chip on our board (using K70) and ran into problems. After power up I see a pattern repeated every four bytes. When I write a byte and read back a block of memory I either don't see any effect or see the test byte repeated on every fourth byte, see attached hexdump. Does this behaviour make any sense? Does it hint at something fundamental?

I don't have access to the control or data lines of the memory chip (BGA package), all I can scope is the clock, which seems to be within specs. The chip does have power and  the cache is disabled. The DDR init script is created by Freescale's K70Memctrl.exe tool,  using a memory configuration based on the memory's datasheet.

How do I go about troubleshooting this issue? Is there any way to further diagnose the problem without access to the control/data lines? I couldn't find any debugging facility in the memory controller.

We might be able to respin our board with test points (avoided them due to space constraints) - what test points should we have? Will the control lines suffice or must have data and/or address lines as well?

Original Attachment has been moved to: shell.txt.zip

[alejandrolozan1]

Hi,

So far the only document I could find are the below application notes.

I hope they are helpful.

•Freescale AppNotes:

−AN2582 Hardware and Layout Design Considerations for DDR Memory Interfaces

−AN2910 Hardware and Layout Design Considerations for DDR2 Memory Interfaces

−AN2583 Programming the PowerQUICCIII / PowerQUICCII Pro DDR SDRAM Controller

−AN3369 PowerQUICC DDR2 SDRAM Controller Register Setting Considerations

  EUF-NET-S0001 DDR Memory Design Consideration – 2010 Malta DFAE training

Best Regards,

Alejandro

[alipoth]

It turns out our problems were due to an (undocumented, I believe) requirement of the memory controller: the DDR must be powered up *before* the DDR clock (PLL1) is set up.

While normally your DDR would be powered up the same as the CPU, therefore the PLL init always happens after DDR power-up, in our case we actively control DDR power, due to power constraints. We tried to make sure the clock was good before powering up the LPDDR chip, which is the wrong approach apparently.

Thanks for the Freescale guys in Austin, TX sorting out this issue for us.