Core Clock divide

[akimata]

Hello,

I've got strange problem using SIM_CLKDIV1 to lower core clock on K80

I'm running PLL on this board and i want to be able to divide high PLL clocks to not exceed bus/core clocks limits.

The problem is if i use this:

SIM -> CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0)| //core
SIM_CLKDIV1_OUTDIV2(1)| // Busclk
SIM_CLKDIV1_OUTDIV3(3)| // FlexBus
SIM_CLKDIV1_OUTDIV4(7)); // Flash

It works, every clock is divided properly but if i try:

SIM -> CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(1)| //core
SIM_CLKDIV1_OUTDIV2(1)| // Busclk
SIM_CLKDIV1_OUTDIV3(3)| // FlexBus
SIM_CLKDIV1_OUTDIV4(7)); // Flash

Write is ignored and i end up with default values. Where is the catch? I read that maximum divide ratio between core and other clocks is 8 but i'm not exceeding this limitations

Thanks for any help :smileyhappy:

[Robin_Shen]

I am using Clocks tool of MCUXpresso IDE, the GPIO example is able to run after modify the divider.

Best Regards,

Robin

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[akimata]

That's really usefull feature in MCUXpresso and now i'm able to set SIM_CLKDIV1 correctly but i noticed that's not perfect.

Not sure if it's bug or i'm doing something wrong but if i want to clock my UART using this tool it's not working properly, wrong clock is selected.

How it's setuped:

Register values in clocks tab :

What i get after i run the code:

And the problem is not only when i want to use PLL to feed UART, it always end up with OSCERCLK clock.

[Robin_Shen]

Please check if there is someplace else select the clock of LPUART again.
For example: the lpuart_interrupt will select OSCERCLK after BOARD_BootClockRUN

Best Regards,

Robin

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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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