Controlling a RGB led with PWM on frdm-k64f

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Controlling a RGB led with PWM on frdm-k64f

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roel0
Contributor II

I have the frdm-k64f and the mbed application shield. On this shield there is a RGB led that I'm trying to control. However nothin happens. It looks like no pules is generated at all.

static inline void RGB_LED(uint32_t red, uint32_t green, uint32_t blue) {

    //FTM0_C5V = red;

    FTM0_C4V = green;

    FTM0_C7V = blue;

}

void frdm_as_led_init() {

    // Power on

    SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTA_MASK;

    SIM_SCGC6 |= SIM_SCGC6_FTM0_MASK;

    //SIM_SOPT4 |= SIM_SOPT4_FTM0TRG0SRC(1);

    //NOTE: multiplexing port pat0 will cause cpu to hard fault on revision other then E

    // because it's also routed to the debugger

    //PORTA_PCR0 = PORT_PCR_MUX(3);  // FTM0_CH5

    PORTC_PCR4 = PORT_PCR_MUX(4);  // FTM0_CH4

    PORTA_PCR2 = PORT_PCR_MUX(3);  // FTM0_CH7

    RGB_LED(0,0,0);

    // Make write_protected registers writable

    FTM0_MODE |= FTM_MODE_WPDIS_MASK;

    FTM0_MODE &= ~ FTM_MODE_FTMEN_MASK;

    // Overflow at 99

    FTM0_MOD  = 99;

    FTM0_CNTIN = 0;

    FTM0_CNT = 0;

    FTM0_C4SC = FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK;

    //FTM0_C5SC = FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK;

    FTM0_C7SC = FTM_CnSC_MSB_MASK | FTM_CnSC_ELSA_MASK | FTM_CnSC_ELSB_MASK;

    FTM0_SC   = FTM_SC_CLKS(1) | FTM_SC_PS(7);     /* Edge Aligned PWM running from BUSCLK / 128 */

    RGB_LED(400,400,400);

}

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Alice_Yang
NXP TechSupport
NXP TechSupport

Hello ,

pastedImage_0.png

pastedImage_1.png

i think the CNT have not run up to 400 , when it up to 99, it overflow .

Hope it helps

Alice

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jeremyzhou
NXP Employee
NXP Employee

Hi Alice,

Alice pointed out the root cause of the issue, and you can find the more information about the value of the CnV setting affects the duty cycle of the PWM pulse in the reference manual.

http://cache.nxp.com/files/microcontrollers/doc/ref_manual/K64P144M120SF5RM.pdf?fpsp=1&WT_TYPE=Refer...
Have a great day,
Ping

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1,473 Views
Alice_Yang
NXP TechSupport
NXP TechSupport

Hello ,

pastedImage_0.png

pastedImage_1.png

i think the CNT have not run up to 400 , when it up to 99, it overflow .

Hope it helps

Alice