Configure WDOG within 128 Bus Clocks Clarification

[sean_dvorscak]

I am experiencing unexpected WDOG behavior according to my understanding of the reference manual in regard to the following:

"All watchdog control bits, timeout value, and window value are write-once after
reset within 128 bus clocks. This means that after a write has occurred they cannot
be changed unless a reset occurs."

My initial interpretation of this is that you must configure the WDOG within the first 128 bus clocks after reset, or it will use the default configuration with UPDATE=0. This will then prevent you from re-configuring the WDOG again.

I however am experiencing something different. Since the KE1 out of reset runs the Bus and Core clock at the same frequency, I decided to look at the CYCLECOUNTER in the IAR debugger when I reconfigure the WDOG, as I thought it would tell me how many bus clocks have also passed since reset. It showed 144 cycles had passed since release from reset. So I started adding longer and longer delay loops at the start of the function to see if it would still allow me to reconfigure well past 144 cycles.

No matter how long the delay, as long as it was below the default 8ms timeout of the WDOG, it would successfully reconfigure the WDOG. I observed this behavior with, and without the debugger, just to ensure the debugger did not play any role. I was also able to confirm timing via strobing the reset signal with Oscope.

So now my understanding of the reference manual is that you can reconfigure the WDOG once out of reset. And once you perform the first write to the WDOG, you get 128 bus clocks to reconfigure the remaining register fields.

For example, lets say I wait 1000 bus clocks out of reset and then configures the WDOG_CS register. I then get 128 bus clocks after configuring the WDOG_CS to configure the WDOG_TOVAL. Once TOVAL is configured, the new configuration takes effect.

Is this the correct interpretation of the reference manual? Or is my previous interpretation correct where you get 128 bus clocks out of reset, or the default configuration takes effect?

[Celeste_Liu · Accepted solution]

Hello @sean_dvorscak ,

Thanks for you post.

You may refer to section "30.4.3.2.1 Unlocking the Watchdog" and section "30.5.2 Configure Watchdog" in KE1xFP100M168SF0RM.

The correct interpretation appears to be as follows:

• After reset, the WDOG is enabled and operates with its reset-default settings.
• The WDOG configuration registers are still available for an initial configuration sequence.
• Once the watchdog is unlocked , the remaining configuration registers must be written within 128 bus clocks .
• If UPDATE=0, then after that initial configuration is completed, the WDOG configuration cannot be changed again until the next reset.
• If UPDATE=1, the WDOG can be unlocked and reconfigured again later, with the same 128 bus clock window applying after each unlock.

This interpretation is consistent with your measurements: even when more than 128 bus clocks had elapsed since reset, the WDOG could still be reconfigured successfully, provided this happened before the default watchdog timeout expired.

In other words, the 128 bus clock configuration window is associated with the unlock sequence, not simply with the elapsed time since reset release.

If no new configuration is completed, the WDOG continues operating with its reset default settings.

Hope it helps.

BR

Celeste

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[sean_dvorscak]

Thank you for the clarification.
Glad to know I have more than 128 bus clocks out of reset to configure WDOG.
If they ever make a new revision of KE1xFP100M168SF0RM, I'd like to suggest removing the "... within 128 bus clocks." from the first sentence of section 30.4.3.1.
Appreciate the suggestion might be silly, but I only suggest it because I found some misinformation online citing that wording to suggest you only get 128 bus clocks to configure WDOG out of reset. It also unfortunately makes the Google AI overview regurgitate the same misinformation (... gotta love the future ). Which is why I had to ask the question here myself.

[Celeste_Liu]

Understood. Unfortunately, to the best of my knowledge, there is no new roadmap for the Kinetis family. We have recently introduced the MCX family, which you may consider exploring if you’re interested. MCX Arm Cortex-M Industrial and IoT MCUs | NXP Semiconductors

[db16122]

There are certain command sequence need to follow in order to update WATCHDOG setting.I dont know where the 128 bus clocks come from but take the K80 Sub-Family Reference Manual, Rev. 4, 09/2015 for example：

As long as ALLOW_UPDATE in the watchdog control register is set, you can unlock and modify the write-once-only control and configuration registers:
1. Write 0xC520 followed by 0xD928 within 20 bus clock cycles to a specific unlock register (WDOG_UNLOCK).
2. Wait one bus clock cycle. You cannot update registers on the bus clock cycle immediately following the write of the unlock sequence.
3. An update window equal in length to the watchdog configuration time (WCT) opens. Within this window, you can update the configuration and control register bits.

These register bits can be modified only once after unlocking.If none of the configuration and control registers is updated within the update window,the watchdog issues a reset, that is, interrupt-then-reset, to the system. Trying to unlock the watchdog within the WCT after an initial unlock has no effect.