Hi
This code will configure the KL16 to run in PEE at 48Mz (24MHz bus/flash) for a 16MHz crystal.
I show the actual register value writes in brackets []:
MCG_C2 = (MCG_C2_RANGE_8M_32M | MCG_C2_GAIN_MODE | MCG_C2_EREFS | MCG_C2_LOCRE0); // [0xa4 for low gain mode or 0xac for high gain mode] select crystal oscillator and select a suitable range
MCG_C1 = (MCG_C1_CLKS_EXTERN_CLK | MCG_C1_FRDIV_512); // [0xa0] switch to external source (the FLL input clock is set to as close to its input range as possible, although this is not absolutely necessary if the FLL will not be used)
while ((MCG_S & MCG_S_OSCINIT) == 0) {} // loop until the crystal source has been selected
while ((MCG_S & MCG_S_IREFST) != 0) {} // loop until the FLL source is no longer the internal reference clock
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_EXTERN_CLK) {} // loop until the external reference clock source is valid
MCG_C5 = ((CLOCK_DIV - 1) | MCG_C5_PLLSTEN0); // [0x27] now move from state FEE to state PBE (or FBE) PLL remains enabled in normal stop modes
MCG_C6 = ((CLOCK_MUL - MCG_C6_VDIV0_LOWEST) | MCG_C6_PLLS); // [0x58] set the PLL multiplication factor
while ((MCG_S & MCG_S_PLLST) == 0) {} // loop until the PLLS clock source becomes valid
while ((MCG_S & MCG_S_LOCK) == 0) {} // loop until PLL locks
SIM_CLKDIV1 = (((SYSTEM_CLOCK_DIVIDE - 1) << 28) | ((BUS_CLOCK_DIVIDE - 1) << 16)); // [0x10010000] prepare bus clock divides
MCG_C1 = (MCG_C1_CLKS_PLL_FLL | MCG_C1_FRDIV_1024); // [0x28] finally move from PBE to PEE mode - switch to PLL clock
while ((MCG_S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL) {} // loop until the PLL clock is selected
Note that the MCG_C2 value depends on whether the crystal circuit needs high or low gain (whether it has feedback resistor and loading capacitors).
If set incorrectly the crystal will not start oscillating and you will get stuck waiting for the crystal source to be selected.
Regards
Mark
KL16/KL26: http://www.utasker.com/kinetis/FRDM-KL26Z.html
MCG: http://www.utasker.com/kinetis/MCG.html
