Clock deviation

[smathad]

Hi NXP community,

I had a few questions regarding the clock deviation using the 48MIRC on the K24. 

Firstly, I understand the from the datasheet that the open loop deviation from 0 to 85 degress is 1%.

Q1. Is it correct to assume that the clock will deviate around 1% (approx. +/- 480000 clocks) between 0 to 85 degrees? Is there some kind of temperature distribution chart for the deviation? 

Q2. How will this clock deviation trickle down to the other clocks, bus clock and flash clock? We want to calculate  effect of clock deviation of each peripheral i.e., SPI, I2C, ADC and UART and in turn compare it with the tolerance given in the datasheet for these peripherals.

Any input will be very much appreciated. 

Thank you

Sachin  

[jingpan]

Hi Sachin,

1. yes, clock will deviate around 1% (approx. +/- 480000 clocks) between 0 to 85 degrees. But there is no such a chart.

2. If you use IRC48 as system clock source, of course it will trickle down to whole system. The deviation is proportional.

Regards,

Jing

[marktverskoy]

Hi, anybody knows what is IRC48 sensitivity to the MCU rail voltage VCC?