I have a project powered with a battery. So in order to reduce power consumption (besides sleep mode) I want to lower the clock frequency.
But in pll_init() I see the following limitations
// Check PLL divider settings are within spec.
if ((prdiv_val < 1) || (prdiv_val > 8)) {return 0x41;}
if ((vdiv_val < 16) || (vdiv_val > 47)) {return 0x42;}
// Check PLL reference clock frequency is within spec.
ref_freq = crystal_val / prdiv_val;
if ((ref_freq < 8000000) || (ref_freq > 32000000)) {return 0x43;}
// Check PLL output frequency is within spec.
pll_freq = (crystal_val / prdiv_val) * vdiv_val;
if ((pll_freq < 180000000) || (pll_freq > 360000000)) {return 0x45;}
The last limitation contradicts others. Or I don't understand something.
What minimum frequency I can get, considering I work with MK70FN1M0VMJ12?
Solved! Go to Solution.
Hi,
The K70 MCG module provides more working mode, the PEE is one working mode using PLL provide the system/core clock. The MCG module supports below working mode:
The K70 PLL output Min. clock frequency is 90MHz:
Customer could consider to use MCG working with FBE mode, which is using external oscillator clock as system/core clock .
Wish it helps.
Have a great day,
Ma Hui
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Hi,
The K70 MCG module provides more working mode, the PEE is one working mode using PLL provide the system/core clock. The MCG module supports below working mode:
The K70 PLL output Min. clock frequency is 90MHz:
Customer could consider to use MCG working with FBE mode, which is using external oscillator clock as system/core clock .
Wish it helps.
Have a great day,
Ma Hui
-----------------------------------------------------------------------------------------------------------------------
Note: If this post answers your question, please click the Correct Answer button. Thank you!
-----------------------------------------------------------------------------------------------------------------------
I see. Thank you.