Clock Loss Interrupt Graceful Transition

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Clock Loss Interrupt Graceful Transition

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norton256
Contributor III

Hello,

I am currently working on a set of custom boards with K60F120 micros. I have a few corner  cases in operation in which the "main" clock on OSC0 may be lost. I would like to enable the Clock Loss interrupt to gracefully transition to a different MCG state without resetting the device.

From which states can one successfully transition to in the interrupt? Also, when a clock loss occurs, how is the device clocked until a new source is selected? Unless I missed it, I did not see any of this documented in the K60 reference manual.

Thanks!

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GordyCarlson
NXP Employee
NXP Employee

Nick,  when you enable the clock loss monitor/interrupt and it then triggers....the K60 will be automatically be clocked by one of the internal reference clocks....either the slow (32Khz IRC) or the fast (2Mhz IRC), depending on how the MCG registers are set up.  See page 550 in the K60 reference manual for detail on FLL bypassed internal (FBI) mode.  

So in your use case.....when the external Real Time Counter (RTC) clock source is lost.......and you have enabled the clock monitor+clock loss interrupt.....it will use the Internal Reference Clock sources (IRC).

A caveat.....if you use STOP, VLPR or VLPW modes, you must disable the Clock Monitor Enable prior to entering any of those modes, otherwise it will trigger a reset request.

About the clearest description I found is section 24.4.4,  but there are so many cross references to other registers/bits that you need to jump around alot to those register descriptions in the reference manual to put all the pieces together.

It would be great to have PDF reference manuals organized like WikiPedia, with embedded links to other sections as noted.  Someday.......

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norton256
Contributor III

OK so to summarize:

The mode switches to FLL Bypassed Internal (FBI). And one of the two internal reference clocks is used based on other MCG register settings at the time of clock loss.

In my particular case where the loss is occurring, it is after I have moved to using OSC0 in either PBE or PEE mode. Does the above still apply?

Thanks!

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GordyCarlson
NXP Employee
NXP Employee

Yes....when enabled the Clock Monitor can be used in any mode that uses the external reference clock... here is a clipping from the Clock Monitor enable bit description in the MCG_C6 register field......

"The CME bit should only be set to a logic 1 when either the MCG is in an operational mode that uses the external clock (FEE, FBE, PEE, PBE, or BLPE) or the external reference is enabled . Whenever the CME bit is set to a logic 1,
the value of the RANGE bits in the C2 register should not be changed. CME bit should be set to a logic 0
before the MCG enters Stop mode. Otherwise, a reset request may occur while in Stop mode."

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