Can bus clock

[songtao8940]

Can bus clock must be based on the bus clock is 50Mhz？

[songtao8940]

first,Thank you for your answer.My can bus part does not work properly with the download function, the communication speed is based on bus clock is 50MHz. Now my bus clock should not 50, I want to know is the 50MHz is not MK20DX128VLH7 this chip the inherent。

[egoodii]

There is no 'inherent' rate for CPU or Bus clock, there are just 'maximums'.  Your general MCG clock setup will determine those.  I recommend running the CAN bit-rate-divisor functions directly from the input (XTAL) clock.

[songtao8940]

Thanks,Another problem is just the welded board with downloader not identify them, what way do

[egoodii]

A CAN interface must be clocked from a accurate source, so 'crystal based', and at a rate AT LEAST 8x bit-rate for 8 quanta (Tq), preferably 16, to place an accurate sample-point 'late' in the bit-cell.  In my systems I start with an 8MHz crystal, and I let the CAN clock run directly from /2 of that to make 250kbit/s J1939.

You seem to have a LOT of questions about how to make CAN work.  I suggest you look at many of the other recent posts about getting CAN to pass full messages,like this one:

https://community.nxp.com/thread/394516

CAN peripherals are very sophisticated standalone communication links, but the downside is that everything has to work 'perfectly' about the interchange to get ANY indication of 'communication' to the CPU.